SLLS980E June   2009  – November 2016 SN75LVDS83A

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (continued)
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Dissipation Ratings
    7. 7.7 Timing Requirements
    8. 7.8 Switching Characteristics
    9. 7.9 Typical Characteristics
  8. Parameter Measurement Information
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 TTL Input Data
      2. 9.3.2 LVDS Output Data
    4. 9.4 Device Functional Modes
      1. 9.4.1 Input Clock Edge
      2. 9.4.2 Low Power Mode
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Signal Connectivity
      2. 10.1.2 PCB Routing
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Power Up Sequence
      3. 10.2.3 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Board Stackup
      2. 12.1.2 Power and Ground Planes
      3. 12.1.3 Traces, Vias, and Other PCB Components
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Receiving Notification of Documentation Updates
    2. 13.2 Community Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

Layout

Layout Guidelines

Board Stackup

There is no fundamental information about how many layers should be used and how the board stackup should look. Again, the easiest way the get good results is to use the design from the EVMs of Texas Instruments. The magazine Elektronik Praxis [11] has published an article with an analysis of different board stackups. These are listed in Table 4.

Table 4. Board Stackup on a Four-Layer PCB

MODEL 1 MODEL 2 MODEL 3 MODEL 4
Layer 1 SIG SIG SIG GND
Layer 2 SIG GND GND SIG
Layer 3 VCC VCC SIG VCC
Layer 4 GND SIG VCC SIG
Decoupling Good Good Bad Bad
EMC Bad Bad Bad Bad
Signal integrity Bad Bad Good Bad
Self disturbance Satisfaction Satisfaction Satisfaction High

Generally, the use of microstrip traces needs at least two layers, whereas one of them must be a GND plane. Better is the use of a four-layer PCB, with a GND and a VCC plane and two signal layers. If the circuit is complex and signals must be routed as stripline, because of propagation delay and/or characteristic impedance, a six-layer stackup should be used.

Power and Ground Planes

A complete ground plane in high-speed design is essential. Additionally, a complete power plane is recommended as well. In a complex system, several regulated voltages can be present. The best solution is for every voltage to have its own layer and its own ground plane. This would result in a huge number of layers just for ground and supply voltages.

In a mixed-signal design (for example, using data converters) the manufacturer often recommends splitting the analog ground and the digital ground to avoid noise coupling between the digital part and the sensitive analog part. Take care when using split ground planes, because the following occurs:

  • Split ground planes act as slot antennas and radiate
  • A routed trace over a gap creates large loop areas, because the return current cannot flow beside the signal. The signal can induce noise into the nonrelated reference plane (see Figure 22).
  • With a proper signal routing, crosstalk also can arise in the return current path due to discontinuities in the ground plane. Always take care of the return current (see Figure 23).

Do not route a signal referenced to digital ground over analog ground and vice versa (see Figure 22). The return current cannot take the direct way along the signal trace and so a loop area occurs. Furthermore, the signal induces noise, due to crosstalk (dotted red line) into the analog ground plane.

SN75LVDS83A lacdpsrgs_SLLS846.gif Figure 22. Loop Area and Crosstalk Due to Poor Signal Routing and Ground Splitting
SN75LVDS83A circp_SLLS846.gif Figure 23. Crosstalk Induced by the Return Current Path

Traces, Vias, and Other PCB Components

A right angle in a trace can cause more radiation. The capacitance increases in the region of the corner, and the characteristic impedance changes. This impedance change causes reflections.

Avoid right-angle bends in a trace and try to route them at least with two 45° corners. To minimize any impedance change, the best routing would be a round bend (see Figure 24).

Separate high-speed signals (for example, clock signals) from low-speed signals and digital from analog signals; again, placement is important.

To minimize crosstalk not only between two signals on one layer but also between adjacent layers, route them with 90° to each other.

SN75LVDS83A pgrab_SLLS846.gif Figure 24. Right Angle Bend Examples

Layout Example

SN75LVDS83A layoutex1_SLLS846.gif Figure 25. SN75LVDS83B EVM Top Layer – TSSOP Package
SN75LVDS83A layoutex2_SLLS846.gif Figure 26. SN75LVDS83B EVM VCC Layer – TSSOP Package