SLLS980E June   2009  – November 2016 SN75LVDS83A

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Dissipation Ratings
    7. 7.7 Timing Requirements
    8. 7.8 Switching Characteristics
    9. 7.9 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 TTL Input Data
      2. 9.3.2 LVDS Output Data
    4. 9.4 Device Functional Modes
      1. 9.4.1 Input Clock Edge
      2. 9.4.2 Low Power Mode
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Signal Connectivity
      2. 10.1.2 PCB Routing
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Power Up Sequence
      3. 10.2.3 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Board Stackup
      2. 12.1.2 Power and Ground Planes
      3. 12.1.3 Traces, Vias, and Other PCB Components
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Receiving Notification of Documentation Updates
    2. 13.2 Community Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

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10 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

10.1 Application Information

This section provides information on device connectivity to various GPU and LCD display panels, and offers a PCB routing example.

10.1.1 Signal Connectivity

While there is no formal industry standardized specification for the input interface of LVDS LCD panels, the industry has aligned over the years on a certain data format (bit order). Figure 14 through Figure 17 show how each signal must be connected from the graphic source through the SN75LVDS83A input, output, and LVDS LCD panel input. Detailed notes are provided with each figure.

SN75LVDS83A lcd_24bit_lls980.gif
A. FORMAT: The majority of 24-bit LCD display panels require the two most significant bits (2 MSB) of each color to be transferred over the 4th serial data output Y3. A few 24-bit LCD display panels require the two LSBs of each color to be transmitted over the Y3 output. The system designer needs to verify which format is expected by checking the LCD display data sheet. Format 1: Use with displays expecting the 2 MSB to be transmitted over the 4th data channel Y3. This is the dominate data format for LCD panels. Format 2: Use with displays expecting the 2 LSB to be transmitted over the 4th data channel.
B. Rpullup: Install only to use rising edge triggered clocking. Rpulldown: Install only to use falling edge triggered clocking. C1: Decoupling capacitor for the VDDIO supply; install at least 1, 0.01-µF capacitor. C2: Decoupling capacitor for the VDD supply; install at least 1, 0.1-µF capacitor and 1, 0.01-µF capacitor. C3: Decoupling capacitor for the VDDPLL and VDDLVDS supply; install at least 1, 0.1-µF capacitor and 1, 0.01-µF capacitor.
C. If RSVD is not driven to a valid logic level, then an external connection to GND is recommended.
D. RSVD must be driven to a valid logic level. All unused SN75LVDS83A inputs must be tied to a valid logic level.
Figure 14. 24-Bit Color Host to 24-Bit LCD Panel Application
SN75LVDS83A lcd_18bit_lls980.gif
A. Leave output Y3 NC.
B. Rpullup: Install only to use rising edge triggered clocking. Rpulldown: Install only to use falling edge triggered clocking. C1: Decoupling capacitor for the VDDIO supply; install at least 1, 0.01-µF capacitor. C2: Decoupling capacitor for the VDD supply; install at least 1, 0.1-µF capacitor and 1, 0.01-µF capacitor. C3: Decoupling capacitor for the VDDPLL and VDDLVDS supply; install at least 1, 0.1-µF capacitor and 1, 0.01-µF capacitor.
Figure 15. 18-Bit Color Host to 18-Bit Color LCD Panel Display Application
SN75LVDS83A lcd_12bit_lls980.gif
A. Leave output Y3 NC.
B. R3, G3, B3: This MSB of each color also connects to the 5th bit of each color for increased dynamic range of the entire color space at the expense of non-linear step sizes between each step. For linear steps with less dynamic range, connect D1, D8, and D18 to GND. R2, G2, B2: These outputs also connect to the LSB of each color for increased. Dynamic range of the entire color space at the expense of non-linear step sizes between each step. For linear steps with less dynamic range, connect D0, D7, and D15 to VCC.
C. Rpullup: Install only to use rising edge triggered clocking. Rpulldown: Install only to use falling edge triggered clocking. C1: Decoupling capacitor for the VDDIO supply; install at least 1, 0.01-µF capacitor. C2: Decoupling capacitor for the VDD supply; install at least 1, 0.1-µF capacitor and 1, 0.01-µF capacitor. C3: Decoupling capacitor for the VDDPLL and VDDLVDS supply; install at least 1, 0.1-µF capacitor and 1, 0.01-µF capacitor.
Figure 16. 12-Bit Color Host to 18-Bit Color LCD Panel Display Application
SN75LVDS83A lcd_24to18bit_lls980.gif
A. Leave output Y3 NC.
B. R0, R1, G0, G1, B0, and B1: For improved image quality, the GPU must dither the 24-bit output pixel down to18-bit per pixel.
C. Rpullup: Install only to use rising edge triggered clocking. Rpulldown: Install only to use falling edge triggered clocking. C1: Decoupling capacitor for the VDDIO supply; install at least 1, 0.01-µF capacitor. C2: Decoupling capacitor for the VDD supply; install at least 1, 0.1-µF capacitor and 1, 0.01-µF capacitor. C3: Decoupling capacitor for the VDDPLL and VDDLVDS supply; install at least 1, 0.1-µF capacitor and 1, 0.01-µF capacitor.
Figure 17. 24-Bit Color Host to 18-Bit Color LCD Panel Display Application

10.1.2 PCB Routing

Figure 18 and Figure 19 show a possible breakout of the data input and output signals from the BGA package.

SN75LVDS83A routing_lls846.gif Figure 18. 24-Bit Color Routing (See Figure 14 for Schematic)
SN75LVDS83A routing2_lls846.gif Figure 19. 18-Bit Color Routing (See Figure 15, Figure 16, and Figure 17 for Schematic)

10.2 Typical Application

Figure 20 represents the schematic drawing of the SN75LVDS83A evaluation module.

SN75LVDS83A schematic_lls980.gif Figure 20. Schematic Example (SN75LVDS83A Evaluation Board)

10.2.1 Design Requirements

Table 3 lists the parameters for this schematic example.

Table 3. Design Parameters

PARAMETER VALUE
VCC 3.3 V
CLKIN Falling edge
SHTDN High
Format 18-bit GPU to 24-bit LCD

10.2.2 Detailed Design Procedure

10.2.2.1 Power Up Sequence

The SN75LVDS83A does not require a specific power up sequence. It is permitted to power up IOVCC while VCC, VCCPLL, and VCCLVDS remain powered down and connected to GND. The input level of the SHTDN during this time does not matter as only the input stage is powered up while all other device blocks are still powered down.

It is also permitted to power up all 3.3-V power domains while IOVCC is still powered down to GND. The device does now suffer damage. However, in this case, all the I/Os are detected as logic HIGH, regardless of their true input voltage level. Therefore, connecting SHTDN to GND is still interpreted as a logic HIGH, and the LVDS output stage are turned on. The power consumption in this condition is significantly higher than standby mode, but still lower than normal mode.

The user experience is impacted by the way a system powers up and powers down an LCD screen. The following sequence is recommended:

Power up sequence (SN75LVDS83A SHTDN input initially low):

  1. Ramp-up LCD power (0.5 ms to 10 ms for example) but keep backlight turned off
  2. Wait an additional 0 to 200 ms to ensure display noise won’t occur
  3. Enable video source output and start sending black video data
  4. Toggle LVDS83A shutdown to SHTDN = VIH
  5. Send >1 ms of black video data (this allows the LVDS83A to be phase locked and the display to show black data first)
  6. Start sending true image data
  7. Enable backlight

Power down sequence (SN75LVDS83A SHTDN input initially high):

  1. Disable LCD backlight and wait for the minimum time specified in the LCD data sheet for the backlight to go low
  2. Video source output data switch from active video data to black image data (all visible pixel turn black); drive this for >2 frame times
  3. Set SN75LVDS83A input SHTDN = GND and wait for 250 ns
  4. Disable the video output of the video source
  5. Remove power from the LCD panel for lowest system power

10.2.3 Application Curve

SN75LVDS83A appcurve_SLLS846.gif Figure 21. 18b GPU to 24b LCD