ZHCSBS6C November 2013 – October 2023 SN74LV1T02
PRODUCTION DATA
9.3.3.2 Up Translation
Input signals can be up translated using the SN74LV1T02. The voltage applied at VCC will determine the output voltage and the input thresholds as described in the Recommended Operating Conditions and Electrical Characteristics tables. When connected to a high-impedance input, the output voltage will be approximately VCC in the HIGH state, and 0 V in the LOW state.
The inputs have reduced thresholds that allow for input high-state levels which are much lower than standard values. For example, standard CMOS inputs for a device operating at a 5-V supply will have a VIH(MIN) of 3.5 V. For the SN74LV1T02, VIH(MIN) with a 5-V supply is only 2 V, which would allow for up-translation from a typical 2.5-V to 5-V signals.
Ensure that the input signals in the HIGH state are above VIH(MIN) and input signals in the LOW state are lower than VIL(MAX) as shown in Figure 9-4.
Up Translation Combinations:
- 1.8-V VCC – Inputs from 1.2 V
- 2.5-V VCC – Inputs from 1.8 V
- 3.3-V VCC – Inputs from 1.8 V and 2.5 V
- 5.0-V VCC – Inputs from 2.5 V and 3.3 V
Figure 9-4 LVxT Up and Down Translation
Example