SLLS753E February   2007  – September 2016 SN65HVD1040-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: Supply Current
    6. 7.6  Electrical Characteristics: Driver
    7. 7.7  Electrical Characteristics: Receiver
    8. 7.8  Switching Characteristics: Device
    9. 7.9  Switching Characteristics: Driver
    10. 7.10 Switching Characteristics: Receiver
    11. 7.11 STB Pin Characteristics
    12. 7.12 SPLIT Pin Characteristics
    13. 7.13 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Mode Control
        1. 9.3.1.1 High-Speed Mode
        2. 9.3.1.2 Low-Power Mode
      2. 9.3.2 Dominant State Time-Out
      3. 9.3.3 Thermal Shutdown
      4. 9.3.4 SPLIT
      5. 9.3.5 Operating Temperature Range
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 CAN Nodes Using Common-Mode Chokes
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
        1. 10.2.1.1 Bus Loading, Length, and Number of Nodes
        2. 10.2.1.2 CAN Termination
        3. 10.2.1.3 Loop Propagation Delay
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 CAN Basics
          1. 10.2.2.1.1 Differential Signal
          2. 10.2.2.1.2 Common-Mode Signal
          3. 10.2.2.1.3 ESD Protection
          4. 10.2.2.1.4 Transient Voltage Suppresser (TVS) Diodes
      3. 10.2.3 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Receiving Notification of Documentation Updates
    2. 13.2 Community Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

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9 Detailed Description

9.1 Overview

The SN65HVD1040-Q1 CAN bus transceiver meets or exceeds the ISO 11898 standard as a high-speed controller area network (CAN) bus physical layer device. The device is designed to interface between the differential bus lines in controller area network and the CAN protocol controller at data rates up to 1 Mbps.

9.2 Functional Block Diagram

SN65HVD1040-Q1 fbd_lls753.gif

9.3 Feature Description

9.3.1 Mode Control

9.3.1.1 High-Speed Mode

Select the high-speed mode of the device operation by setting the STB pin low. The CAN bus driver and receiver are fully operational and the CAN communication is bidirectional. The driver is translating a digital input on TXD to a differential output on CANH and CANL. The receiver is translating the differential signal from CANH and CANL to a digital output on RXD.

9.3.1.2 Low-Power Mode

If a high logic level is applied to the STB pin, the device enters a low-power bus-monitor standby mode. While the SN65HVD1040-Q1 is in the low-power bus-monitor standby mode, a dominant bit greater than 5 µs on the bus is passed by the bus-monitor circuit to the receiver output. The local protocol controller may then reactivate the device when it needs to transmit to the bus.

9.3.2 Dominant State Time-Out

During normal mode, the mode where the CAN driver is active, the TXD DTO circuit prevents the transceiver from blocking network communication in the event of a hardware or software failure where TXD is held dominant longer than the time-out period tTXD_DTO. The DTO circuit is triggered on a falling edge on the driver input, TXD. The DTO circuit disables the CAN bus driver if no rising edge is seen on TXD before the time-out period expires. This frees the CAN bus for communication between other nodes on the network. The CAN driver is re-enabled when a rising edge is seen on the driver input, TXD, thus clearing the TXD DTO condition. The receiver and RXD pin still reflect the CAN bus, and the bus pins are biased to recessive level during a TXD DTO.

NOTE

The minimum dominant TXD time allowed by the TXD DTO circuit limits the minimum possible transmitted data rate on the device. The CAN protocol allows a maximum of eleven successive dominant bits (on TXD) for the worst case, where five successive dominant bits are followed immediately by an error frame. This, along with the tTXD_DTO minimum, limits the minimum data rate. Calculate the minimum transmitted data rate using: Minimum Data Rate = 11 / tTXD_DTO.

9.3.3 Thermal Shutdown

The SN65HVD1040-Q1 device has a thermal shutdown that turns off the driver outputs when the junction temperature nears 190°C. This shutdown prevents catastrophic failure from bus shorts, but does not protect the circuit from possible damage. The user should strive to maintain recommended operating conditions, and not exceed absolute maximum ratings at all times. If the SN65HVD1040-Q1 device is subjected to many or long durations faults that can put the device into thermal shutdown, it must be replaced.

9.3.4 SPLIT

A reference voltage (VCC/2) is available through the SPLIT output pin. The SPLIT voltage must be tied to the common-mode point in a split termination network, hence the pin name, to help stabilize the output common-mode voltage. See Figure 28 for more application specific information on properly terminating the CAN bus.

SN65HVD1040-Q1 split_pin_stabil.gif Figure 24. SPLIT Pin Stabilization Circuitry and Application

9.3.5 Operating Temperature Range

The SN65HVD1040-Q1 is characterized for operation from –40°C to 125°C.

9.4 Device Functional Modes

Table 2 and Table 3 lists the functional modes of the SN65HVD1040-Q1.

Table 2. Driver Function Table(1)

INPUTS OUTPUTS BUS STATE
TXD STB CANH CANL
L L H L Dominant
H L Z Z Recessive
Open L Z Z Recessive
X H or Open Y Y Recessive
(1) H = high level, L = low level, X = irrelevant, ? = indeterminate, Y = weak pulldown do GND, Z = high impedance

Table 3. Receiver Function Table(1)

DIFFERENTIAL INPUTS
VID = V(CANH) – V(CANL)		 STB OUTPUT
RXD		 BUS STATE
VID ≥ 0.9 V L L Dominant
VID ≥ 1.15 V H or Open L Dominant
0.5 V < VID < 0.9 V X ? ?
VID ≤ 0.5 V X H Recessive
Open X H Recessive
(1) H = high level, L = low level, X = irrelevant, ? = indeterminate, Z = high impedance

Table 4. Parametric Cross Reference With the TJA1040

TJA1040(1) PARAMETER HVD10xx
TJA1040 DRIVER SECTION
VIH High-level input voltage Recommended VIH
VIL Low-level input voltage Recommended VIL
IIH High-level input current Driver IIH
IIL Low-level input current Driver IIL
TJA1040 BUS SECTION
Vth(dif) Differential input voltage Receiver VIT and recommended VID
Vhys(dif) Differential input hysteresis Receiver Vhys
VO(dom) Dominant output voltage Driver VO(D)
VO(reces) Recessive output voltage Driver VO(R)
VI(dif)(th) Differential input voltage Receiver VIT and recommended VID
VO(dif0(bus) Differential bus voltage Driver VOD(D) and VOD(R)
ILI Power-off bus input current Receiver II(off)
IO(SC) Short-circuit output current Driver IOS(SS)
RI(cm) CANH, CANL input resistance Receiver RIN
RI(def) Differential input resistance Receiver RID
RI(cm) (m) Input resistance matching Receiver RI (m)
CI(cm) Input capacitance to ground Receiver CI
CI(dif) Differential input capacitance Receiver CID
TJA1040 RECEIVER SECTION
IOH High-level output current Recommended IOH
IOL Low-level output current Recommended IOL
TJA1040 SPLIT PIN SECTION
VO Reference output voltage VO
TJA1040 TIMING SECTION
td(TXD-BUSon) Delay TXD to bus active Driver tPLH
td(TXD-BUSoff) Delay TXD to bus inactive Driver tPHL
td(BUSon-RXD) Delay bus active to RXD Receiver tPHL
td(BUSoff-RXD) Delay bus inactive to RXD Receiver tPLH
tPD(TXD–RXD) Prop delay TXD to RXD Device tLOOP1 and tLOOP2
td(stb-norm) Enable time from standby to dominant Driver ten
TJA1040 STB PIN SECTION
VIH High-level input voltage Recommended VIH
VIL Low-level input voltage Recommended VIL
IIH High-level input current IIH
IIL Low-level input current IIL
(1) From TJA1040 Product Specification, NXP, February 19, 2003.
SN65HVD1040-Q1 equiv_io_cxs_lls753.gif Figure 25. Equivalent Input and Output Schematic Diagrams