ZHCSF35A October   2014  – June 2016 PGA300

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - Reverse Voltage Protection
    6. 6.6  Electrical Characteristics - Regulators
    7. 6.7  Electrical Characteristics - Internal Reference
    8. 6.8  Electrical Characteristics - Bridge Sensor Supply
    9. 6.9  Electrical Characteristics - Temperature Sensor Supply
    10. 6.10 Electrical Characteristics - Internal Temperature Sensor
    11. 6.11 Electrical Characteristics - P Gain (Chopper Stabilized)
    12. 6.12 Electrical Characteristics - P Analog-to-Digital Converter
    13. 6.13 Electrical Characteristics - T Gain (Chopper Stabilized)
    14. 6.14 Electrical Characteristics - T Analog-to-Digital Converter
    15. 6.15 Electrical Characteristics - One-Wire Interface
    16. 6.16 Electrical Characteristics - DAC Output
    17. 6.17 Electrical Characteristics - DAC Gain
    18. 6.18 Electrical Characteristics - Non-Volatile Memory
    19. 6.19 Electrical Characteristics - Diagnostics
    20. 6.20 Operating Characteristics
    21. 6.21 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Reverse-Voltage Protection Block
      2. 7.3.2  Linear Regulators
      3. 7.3.3  Internal Reference
        1. 7.3.3.1 High-Voltage Reference
        2. 7.3.3.2 Accurate Reference
      4. 7.3.4  BRG+ to BRG- Supply for the Resistive Bridge
      5. 7.3.5  ITEMP Supply for the Temperature Sensor
      6. 7.3.6  Internal Temperature Sensor
      7. 7.3.7  P Gain
      8. 7.3.8  P Analog-to-Digital Converter
        1. 7.3.8.1 P Sigma-Delta Modulator for P ADC
        2. 7.3.8.2 P Decimation Filter for P ADC
      9. 7.3.9  T Gain
      10. 7.3.10 T Analog-to-Digital Converter
        1. 7.3.10.1 T Sigma-Delta Modulator for T ADC
        2. 7.3.10.2 T Decimation Filters for T ADC
      11. 7.3.11 P GAIN and T GAIN Calibration
      12. 7.3.12 One-Wire Interface (OWI)
        1. 7.3.12.1 Overview of OWI
        2. 7.3.12.2 Activating and Deactivating the OWI Interface
          1. 7.3.12.2.1 Activating OWI Communication
          2. 7.3.12.2.2 Deactivating OWI Communication
        3. 7.3.12.3 OWI Protocol
          1. 7.3.12.3.1 OWI Frame Structure
            1. 7.3.12.3.1.1 Standard Field Structure
            2. 7.3.12.3.1.2 Frame Structure
            3. 7.3.12.3.1.3 Sync Field
            4. 7.3.12.3.1.4 Command Field
            5. 7.3.12.3.1.5 Data Fields
          2. 7.3.12.3.2 OWI Commands
            1. 7.3.12.3.2.1 OWI Write Command
            2. 7.3.12.3.2.2 OWI Read Initialization Command
            3. 7.3.12.3.2.3 OWI Read-Response Command
            4. 7.3.12.3.2.4 OWI Burst-Write Command (EEPROM Cache Access)
            5. 7.3.12.3.2.5 OWI Burst Read Command (EEPROM Cache Access)
          3. 7.3.12.3.3 OWI Operations
            1. 7.3.12.3.3.1 Write Operation
            2. 7.3.12.3.3.2 Read Operation
            3. 7.3.12.3.3.3 EEPROM Burst Write
            4. 7.3.12.3.3.4 EEPROM Burst Read
        4. 7.3.12.4 OWI Communication-Error Status
      13. 7.3.13 DAC Output
        1. 7.3.13.1 Ratiometric vs Absolute
      14. 7.3.14 DAC Gain
      15. 7.3.15 Memory
        1. 7.3.15.1 EEPROM Memory
          1. 7.3.15.1.1 EEPROM Cache
          2. 7.3.15.1.2 EEPROM Programming Procedure
          3. 7.3.15.1.3 EEPROM Programming Current
          4. 7.3.15.1.4 CRC
        2. 7.3.15.2 Control and Status Registers Memory
      16. 7.3.16 Diagnostics
        1. 7.3.16.1 Power Supply Diagnostics
        2. 7.3.16.2 Signal Chain Faults
          1. 7.3.16.2.1 P Gain and T Gain Input Faults
          2. 7.3.16.2.2 P Gain and T Gain Output Diagnostics
          3. 7.3.16.2.3 Masking Signal Chain Faults
          4. 7.3.16.2.4 Fault Detection Timing
      17. 7.3.17 Digital Compensation and Filter
        1. 7.3.17.1 Digital Gain and Offset
        2. 7.3.17.2 TC and NL Correction
          1. 7.3.17.2.1 TC and NL Coefficients
            1. 7.3.17.2.1.1 No TC and NL Coefficients
          2. 7.3.17.2.2 TC Compensation Using the Internal Temperature Sensor
        3. 7.3.17.3 Clamping
        4. 7.3.17.4 Filter
      18. 7.3.18 Filter Coefficients
        1. 7.3.18.1 No Filtering
        2. 7.3.18.2 Filter Coefficients for P ADC Sampling Rate = 128 µs
    4. 7.4 Device Functional Modes
      1. 7.4.1 Voltage Mode
      2. 7.4.2 Current Mode
    5. 7.5 Register Maps
      1. 7.5.1 Register Settings
      2. 7.5.2 Control and Status Registers
        1. 7.5.2.1  DAC_CONFIG
        2. 7.5.2.2  OP_STAGE_CTRL
        3. 7.5.2.3  BRDG_CTRL
        4. 7.5.2.4  P_GAIN_SELECT
        5. 7.5.2.5  T_GAIN_SELECT
        6. 7.5.2.6  TEMP_CTRL
        7. 7.5.2.7  TEMP_SE
        8. 7.5.2.8  DIAG_ENABLE
        9. 7.5.2.9  AFEDIAG_CFG
        10. 7.5.2.10 AFEDIAG_MASK
        11. 7.5.2.11 COMPENSATION_CONTROL
        12. 7.5.2.12 EEPROM_LOCK
        13. 7.5.2.13 EEPROM_PAGE_ADDRESS
        14. 7.5.2.14 EEPROM_CTRL
        15. 7.5.2.15 EEPROM_CRC
        16. 7.5.2.16 EEPROM_STATUS
        17. 7.5.2.17 EEPROM_CRC_STATUS
        18. 7.5.2.18 EEPROM_CRC_VALUE
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 4-mA to 20-mA Output With Internal Sense Resistor
        1. 8.1.1.1 Design Requirements
        2. 8.1.1.2 Detailed Design Procedure
          1. 8.1.1.2.1 Calibration Tips
            1. 8.1.1.2.1.1 Programming the EEPROM for 4-mA to 20-mA Output
        3. 8.1.1.3 Application Curve
      2. 8.1.2 0- to 10-V Absolute Output With Internal Drive
        1. 8.1.2.1 Design Requirements
        2. 8.1.2.2 Detailed Design Procedure
          1. 8.1.2.2.1 Programmer Tips
            1. 8.1.2.2.1.1 Resetting the Microprocessor and Enable Digital Interface
            2. 8.1.2.2.1.2 Turning On the Accurate Reference Buffer (REFCAP Voltage)
            3. 8.1.2.2.1.3 Turning On DAC and DAC GAIN
      3. 8.1.3 0- to 5-V Ratiometric Output With Internal Drive
        1. 8.1.3.1 Design Requirements
        2. 8.1.3.2 Detailed Design Procedure
          1. 8.1.3.2.1 Programmer Tips
            1. 8.1.3.2.1.1 Resetting the Microprocessor and Enable Digital Interface
            2. 8.1.3.2.1.2 Turning On the Accurate Reference Buffer (REFCAP Voltage)
            3. 8.1.3.2.1.3 Turning On DAC and DAC GAIN
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 商标
    2. 11.2 静电放电警告
    3. 11.3 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

The PGA 300 can be used in a variety of applications to measure pressure and temperature. Depending on the application, the device can be configured in different modes as illustrated in the following sections.

8.1.1 4-mA to 20-mA Output With Internal Sense Resistor

PGA300 app_4_20mA_SLDS204.gif Figure 40. 4-mA to 20-mA Output With Internal Sense Resistor Diagram

8.1.1.1 Design Requirements

There are only a few requirements to take into account when using the PGA300 device in a design:

  • Do not exceed the maximum slew rate of 0.5 V/µs at the PWR pin.
  • Place a 100-nF capacitor from the AVDD pin to ground, as close as possible to the AVDD pin.
  • Place a 100-nF capacitor from the DVDD pin to ground, as close as possible to the DVDD pin.
  • Place a capacitor between 10 nF and 1000 nF from the REFCAP pin to ground, as close as possible to the REFCAP pin.
  • Place a 150-Ω resistor between the COMP pin and the emitter of the BJT for current-loop stability purposes.
  • Place a 10-Ω resistor between the FB+ pin and the negative terminal of the controller for current measurement.

8.1.1.2 Detailed Design Procedure

8.1.1.2.1 Calibration Tips

8.1.1.2.1.1 Programming the EEPROM for 4-mA to 20-mA Output

The EEPROM in the PGA300 is configured by default to operate in current mode using the OP_STG_CTRL register. If not, the following sequence must be followed to change it to current mode:

  1. Send an OWI activation pulse to stop the digital compensation from running.
  2. Set OP_STAGE_CTRL to 0x80 for current mode and DAC_CONFIG EEPROM to 0x00 or 0x01 for No_Gain.
  3. Let the digital compensation run again to read the new EEPROM values.

8.1.1.3 Application Curve

PGA300 Typical_app_current.gif
Voltage measured between the GND pin in the PGA300 device and the negative terminal of the controller. This includes the internal 40-Ω resistor and an external 10-Ω resistor, VPWR = 15 V. The DAC codes used were 0x880 and 0x2760 for 4 mA and 20 mA, respectively.
Figure 41. Loop Current Step From 4 mA to 20 mA

8.1.2 0- to 10-V Absolute Output With Internal Drive

PGA300 app_0_10V_abs_SLDS204.gif Figure 42. 0- to 10-V Absolute Output With Internal Drive Diagram

8.1.2.1 Design Requirements

There are only a few requirements to take into account when using the PGA300 in a design:

  • Do not exceed the maximum slew rate of 0.5 V/µs at the VDD pin.
  • Place a 100-nF capacitor from the AVDD pin to ground, as close as possible to the AVDD pin.
  • Place a 100-nF capacitor from the DVDD pin to ground, as close as possible to the DVDD pin.
  • Place a capacitor between 10 nF and 1000 nF from the REFCAP pin to ground, as close as possible to the REFCAP pin.
  • Implement compensation, using the COMP pin and an isolation resistor, when driving large capacitive loads with the OUT pin.

8.1.2.2 Detailed Design Procedure

8.1.2.2.1 Programmer Tips

8.1.2.2.1.1 Resetting the Microprocessor and Enable Digital Interface

The following bits must be configured to reset the M0 microprocessor and to enable digital interface:

  1. Set the IF_SEL bit in the MICRO_INTERFACE_CONTROL register to 1.
  2. Set the MICRO_RESET bit in the MICRO_INTERFACE_CONTROL register to 1.

8.1.2.2.1.2 Turning On the Accurate Reference Buffer (REFCAP Voltage)

The following bits must be configured to turn ON the accurate reference buffer:

  1. Set the SD bit in the ALPWR register to 0.
  2. Set the ADC_EN_VREF bit in the ALPWR register to 1.

By turning on the accurate reference buffer, the reference voltage can be measured on REFCAP pin. Further, the capacitor on the REFCAP pin is connected to the reference buffer.

8.1.2.2.1.3 Turning On DAC and DAC GAIN

The following bits must be configured to turn on DAC and DAC GAIN:

  • Set the SD bit in the ALPWR register to 0.
  • Set the ADC_EN_VREF bit in the ALPWR register to 1.
  • Set the DAC_ENABLE bit in the DAC_CTRL_STATUS register to 1.
  • Set the 4_20_MA_EN bit in the OP_STAGE_CTRL register for voltage output or current output mode.
  • Set the DACCAP_EN bit in the OP_STAGE_CTRL register to connect or disconnect the external capacitor at the DAC output.
  • Set the DAC_RATIOMETRIC bit in the DAC_CONFIG register for ratiometric or absolute-voltage output mode.
  • Set the TEST_MUX_DAC_EN bit in the AMUX_CTRL register to 1.

8.1.3 0- to 5-V Ratiometric Output With Internal Drive

PGA300 app_0_5V_rat_SLDS204.gif Figure 43. 0- to 5-V Ratiometric Output With Internal Drive Diagram

8.1.3.1 Design Requirements

There are only a few requirements to take into account when using the PGA300 in a design:

  • Do not exceed the maximum slew rate of 0.5 V/µs at the PWR pin.
  • Place a 100-nF capacitor from the AVDD pin to ground, as close as possible to the AVDD pin.
  • Place a 100-nF capacitor from the DVDD pin to ground, as close as possible to the DVDD pin.
  • Place a capacitor between 10 nF and 1000 nF from the REFCAP pin to ground, as close as possible to the REFCAP pin.
  • Implement compensation, using the COMP pin and an isolation resistor, when driving large capacitive loads with the OUT pin.

8.1.3.2 Detailed Design Procedure

8.1.3.2.1 Programmer Tips

8.1.3.2.1.1 Resetting the Microprocessor and Enable Digital Interface

The following bits must be configured to reset the M0 microprocessor and to enable digital interface:

  1. Set the IF_SEL bit in the MICRO_INTERFACE_CONTROL register to 1.
  2. Set the MICRO_RESET bit in the MICRO_INTERFACE_CONTROL register to 1.

8.1.3.2.1.2 Turning On the Accurate Reference Buffer (REFCAP Voltage)

The following bits must be configured to turn ON the accurate reference buffer:

  1. Set the SD bit in the ALPWR register to 0.
  2. Set the ADC_EN_VREF bit in the ALPWR register to 1.

By turning on the accurate reference buffer, the reference voltage can be measured on REFCAP pin. Further, the capacitor on the REFCAP pin is connected to the reference buffer.

8.1.3.2.1.3 Turning On DAC and DAC GAIN

The following bits must be configured to turn on DAC and DAC GAIN:

  • Set the SD bit in ALPWR register to 0.
  • Set the ADC_EN_VREF bit in the ALPWR register to 1.
  • Set the DAC_ENABLE bit in the DAC_CTRL_STATUS register to 1.
  • Set the 4_20_MA_EN bit in the OP_STAGE_CTRL register for the voltage-output or current-output mode.
  • Set the DACCAP_EN bit in the OP_STAGE_CTRL register to connect or disconnect the external capacitor at the DAC output.
  • Set the DAC_RATIOMETRIC bit in the DAC_CONFIG register for ratiometric or absolute-voltage output mode.
  • Set the TEST_MUX_DAC_EN bit in the AMUX_CTRL register to 1.