ZHCSLE3 June   2023 OPT4060

PRODUCTION DATA  

  1.   1
  2. 特性
  3. 应用
  4. 说明
  5. Revision History
  6. 说明(续)
  7. Pin Configuration and Functions
  8. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  9. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Infrared Light Rejection
      2. 8.3.2 Automatic Full-Scale Range Setting
      3. 8.3.3 Output Register CRC and Counter
        1. 8.3.3.1 Output Sample Counter
        2. 8.3.3.2 Output CRC
        3. 8.3.3.3 Threshold Detection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Modes of Operation
      2. 8.4.2 Interrupt Modes of Operation
      3. 8.4.3 Light Range Selection
      4. 8.4.4 Selecting Conversion Time
      5. 8.4.5 Light and Color Measurement
        1. 8.4.5.1 Determining ADC Codes for Each Channel
        2. 8.4.5.2 Lux and Color Calculations
        3. 8.4.5.3 Threshold Detection Calculations
      6. 8.4.6 Light Resolution
    5. 8.5 Programming
      1. 8.5.1 I2C Bus Overview
        1. 8.5.1.1 Serial Bus Address
        2. 8.5.1.2 Serial Interface
      2. 8.5.2 Writing and Reading
        1. 8.5.2.1 High-Speed I2C Mode
        2. 8.5.2.2 Burst Read Mode
        3. 8.5.2.3 General-Call Reset Command
        4. 8.5.2.4 SMBus Alert Response
    6. 8.6 Register Maps
      1. 8.6.1 Register Map
  10. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Electrical Interface
        1. 9.2.1.1 Design Requirements
          1. 9.2.1.1.1 Optical Interface
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Optomechanical Design
        3. 9.2.1.3 Application Curve
    3. 9.3 Best Design Practices
    4. 9.4 Power Supply Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
      3. 9.5.3 Soldering and Handling Recommendations
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 接收文档更新通知
    3. 10.3 支持资源
    4. 10.4 Trademarks
    5. 10.5 静电放电警告
    6. 10.6 术语表
  12. 11Mechanical, Packaging, and Orderable Information

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订购信息

Writing and Reading

Accessing a specific register on the OPT4060 is accomplished by writing the appropriate register address during the I2C transaction sequence. Refer to the Register Maps for a complete list of registers and their corresponding register addresses. The value for the register address (as shown in Register Maps) is the first byte transferred after the target address byte with the R/W bit low.

GUID-20221205-SS0I-8F07-XN7M-QD5TDW32J3VG-low.svg Figure 8-3 Setting the I2C Register Address

Writing to a register begins with the first byte transmitted by the controller. This byte is the target address with the R/W bit low. The device then acknowledges receipt of a valid address. The register address the data will write to is the next byte transmitted by the controller. The next two bytes are written to the register addressed by the register address. The device acknowledges receipt of each data byte. The controller can terminate the data transfer by generating a start or stop condition.

When reading from the device, the last value stored in the register address by a write operation determines which register is read during a read operation. To change the register address for a read operation, a new partial I2C write transaction must be initiated. This partial write is accomplished by issuing a target address byte with the R/W bit low, followed by the register address byte and a stop command. The controller then generates a start condition and sends the target address byte with the R/W bit high to initiate the read command. The next byte is transmitted by the target and is the most significant byte of the register indicated by the register address. This byte is followed by an acknowledge from the controller; then the target transmits the least significant byte. The controller acknowledges receipt of the data byte. The controller can terminate the data transfer by generating a not-acknowledge after receiving any data byte, or by generating a start or stop condition. If repeated reads from the same register are desired, continually sending the register address bytes is not necessary; the device retains the register address until that number is changed by the next write operation.

Figure 8-4 and Figure 8-5 show the write and read operation timing diagrams, respectively. Note that register bytes are sent most significant byte first, followed by the least significant byte.

GUID-20221205-SS0I-V1QH-ZRBN-WNQLT2HD6D2V-low.svg Figure 8-4 I2C Write Example
GUID-20221205-SS0I-BDSR-HNBT-STTC2NQRLXCM-low.svg
An ACK by the controller can also be sent.
Figure 8-5 I2C Read Example