ZHCSDF6F October   2014  – December 2021 MSP430FR4131 , MSP430FR4132 , MSP430FR4133

PRODUCTION DATA  

  1. 特性
  2. 应用
  3. 说明
  4. 功能方框图
  5. Revision History
  6. Device Comparison
    1. 6.1 Related Products
  7. Terminal Configuration and Functions
    1. 7.1 Pin Diagrams
    2. 7.2 Signal Descriptions
    3. 7.3 Pin Multiplexing
    4. 7.4 Connection of Unused Pins
  8. Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 8.5  Active Mode Supply Current Per MHz
    6. 8.6  Low-Power Mode LPM0 Supply Currents Into VCC Excluding External Current
    7. 8.7  Low-Power Mode LPM3, LPM4 Supply Currents (Into VCC) Excluding External Current
    8. 8.8  Low-Power Mode LPMx.5 Supply Currents (Into VCC) Excluding External Current
    9. 8.9  Typical Characteristics, Low-Power Mode Supply Currents
    10. 8.10 Current Consumption Per Module
    11. 8.11 Thermal Characteristics
    12. 8.12 Timing and Switching Characteristics
      1. 8.12.1  Power Supply Sequencing
        1. 8.12.1.1 PMM, SVS and BOR
      2. 8.12.2  Reset Timing
        1. 8.12.2.1 Wake-up Times From Low-Power Modes and Reset
      3. 8.12.3  Clock Specifications
        1. 8.12.3.1 XT1 Crystal Oscillator (Low Frequency)
        2. 8.12.3.2 DCO FLL, Frequency
        3. 8.12.3.3 REFO
        4. 8.12.3.4 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
        5. 8.12.3.5 Module Oscillator Clock (MODCLK)
      4. 8.12.4  Digital I/Os
        1. 8.12.4.1 Digital Inputs
        2. 8.12.4.2 Digital Outputs
        3. 8.12.4.3 Digital I/O Typical Characteristics
      5. 8.12.5  Timer_A
        1. 8.12.5.1 Timer_A
      6. 8.12.6  eUSCI
        1. 8.12.6.1 eUSCI (UART Mode) Operating Frequency
        2. 8.12.6.2 eUSCI (UART Mode) Switching Characteristics
        3. 8.12.6.3 eUSCI (SPI Master Mode) Operating Frequency
        4. 8.12.6.4 eUSCI (SPI Master Mode) Switching Characteristics
        5. 8.12.6.5 eUSCI (SPI Slave Mode) Switching Characteristics
        6. 8.12.6.6 eUSCI (I2C Mode) Switching Characteristics
      7. 8.12.7  ADC
        1. 8.12.7.1 ADC, Power Supply and Input Range Conditions
        2. 8.12.7.2 ADC, 10-Bit Timing Parameters
        3. 8.12.7.3 ADC, 10-Bit Linearity Parameters
      8. 8.12.8  LCD Controller
        1. 8.12.8.1 LCD Recommended Operating Conditions
      9. 8.12.9  FRAM
        1. 8.12.9.1 FRAM
      10. 8.12.10 Emulation and Debug
        1. 8.12.10.1 JTAG and Spy-Bi-Wire Interface
  9. Detailed Description
    1. 9.1  CPU
    2. 9.2  Operating Modes
    3. 9.3  Interrupt Vector Addresses
    4. 9.4  Bootloader (BSL)
    5. 9.5  JTAG Standard Interface
    6. 9.6  Spy-Bi-Wire Interface (SBW)
    7. 9.7  FRAM
    8. 9.8  Memory Protection
    9. 9.9  Peripherals
      1. 9.9.1  Power Management Module (PMM) and On-Chip Reference Voltages
      2. 9.9.2  Clock System (CS) and Clock Distribution
      3. 9.9.3  General-Purpose Input/Output Port (I/O)
      4. 9.9.4  Watchdog Timer (WDT)
      5. 9.9.5  System Module (SYS)
      6. 9.9.6  Cyclic Redundancy Check (CRC)
      7. 9.9.7  Enhanced Universal Serial Communication Interface (eUSCI_A0, eUSCI_B0)
      8. 9.9.8  Timers (Timer0_A3, Timer1_A3)
      9. 9.9.9  Real-Time Clock (RTC) Counter
      10. 9.9.10 10-Bit Analog Digital Converter (ADC)
      11. 9.9.11 Liquid Crystal Display (LCD)
      12. 9.9.12 Embedded Emulation Module (EEM)
      13. 9.9.13 Input/Output Schematics
        1. 9.9.13.1  Port P1 Input/Output With Schmitt Trigger
        2. 9.9.13.2  Port P2 Input/Output With Schmitt Trigger
        3. 9.9.13.3  Port P3 Input/Output With Schmitt Trigger
        4. 9.9.13.4  Port P4.0 Input/Output With Schmitt Trigger
        5. 9.9.13.5  Port P4.1 and P4.2 Input/Output With Schmitt Trigger
        6. 9.9.13.6  Port 4.3, P4.4, P4.5, P4.6, and P4.7 Input/Output With Schmitt Trigger
        7. 9.9.13.7  Port P5.0, P5.1, P5.2, and P5.3 Input/Output With Schmitt Trigger
        8. 9.9.13.8  Port P5.4, P5.5, P5.6, and P5.7 Input/Output With Schmitt Trigger
        9. 9.9.13.9  Port P6 Input/Output With Schmitt Trigger
        10. 9.9.13.10 Port P7 Input/Output With Schmitt Trigger
        11. 9.9.13.11 Port P8.0 and P8.1 Input/Output With Schmitt Trigger
        12. 9.9.13.12 Port P8.2 and P8.3 Input/Output With Schmitt Trigger
    10. 9.10 Device Descriptors (TLV)
    11. 9.11 Memory
      1. 9.11.1 Peripheral File Map
    12. 9.12 Identification
      1. 9.12.1 Revision Identification
      2. 9.12.2 Device Identification
      3. 9.12.3 JTAG Identification
  10. 10Applications, Implementation, and Layout
    1. 10.1 Device Connection and Layout Fundamentals
      1. 10.1.1 Power Supply Decoupling and Bulk Capacitors
      2. 10.1.2 External Oscillator
      3. 10.1.3 JTAG
      4. 10.1.4 Reset
      5. 10.1.5 Unused Pins
      6. 10.1.6 General Layout Recommendations
      7. 10.1.7 Do's and Don'ts
    2. 10.2 Peripheral- and Interface-Specific Design Information
      1. 10.2.1 ADC Peripheral
        1. 10.2.1.1 Partial Schematic
        2. 10.2.1.2 Design Requirements
        3. 10.2.1.3 Layout Guidelines
      2. 10.2.2 LCD_E Peripheral
        1. 10.2.2.1 Partial Schematic
        2. 10.2.2.2 Design Requirements
        3. 10.2.2.3 Detailed Design Procedure
        4. 10.2.2.4 Layout Guidelines
      3. 10.2.3 Timer
        1. 10.2.3.1 Generate Accurate PWM Using Internal Oscillator
    3. 10.3 Typical Applications
  11. 11Device and Documentation Support
    1. 11.1 Getting Started
    2. 11.2 Device Nomenclature
    3. 11.3 Tools and Software
    4. 11.4 Documentation Support
    5. 11.5 支持资源
    6. 11.6 Trademarks
    7. 11.7 Electrostatic Discharge Caution
    8. 11.8 Export Control Notice
    9. 11.9 术语表
  12. 12Mechanical, Packaging, and Orderable Information

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Revision History

Changes from revision E to revision F

Changes from December 9, 2019 to December 8, 2021

  • 更新了整个文档中的表格、图和交叉参考的编号格式。Go
  • Added Section 10.2.3.1 Generate Accurate PWM Using Internal Oscillator Go

Changes from revision D to revision E

Changes from January 22, 2019 to December 9, 2019

  • Changed the note that begins "Supply voltage changes faster than 0.2 V/µs can trigger a BOR reset..." in Section 8.3, Recommended Operating Conditions Go
  • Added the note that begins "TI recommends that power to the DVCC pin must not exceed the limits..." in Section 8.3, Recommended Operating Conditions Go
  • Changed the note that begins "A capacitor tolerance of ±20% or better is required..." in Section 8.3, Recommended Operating Conditions Go
  • Added the note "See MSP430 32-kHz Crystal Oscillators for details on crystal section, layout, and testing" to Section 8.12.3.1, XT1 Crystal Oscillator (Low Frequency) Go
  • Changed the note that begins "Requires external capacitors at both terminals..." in Section 8.12.3.1, XT1 Crystal Oscillator (Low Frequency) Go
  • Added the t(int) parameter in Section 8.12.4.1, Digital Inputs Go
  • Added the tTA,capparameter in Section 8.12.5.1, Timer_A Go
  • Corrected the test conditions for the RI,MUX parameter in Section 8.12.7.1, ADC, Power Supply and Input Range Conditions Go
  • Added the note that begins "tSample = ln(2n+1) × τ ..." in Section 8.12.7.2, ADC, 10-Bit Timing Parameters Go

Changes from revision C to revision D

Changes from August 30, 2018 to January 21, 2019

  • 通篇将“调制振荡器 (MODOSC)”更改为“调制振荡器时钟 (MODCLK)”Go
  • Added "or memory corruption" in table that starts "Stresses beyond those listed..." of Section 8.1, Absolute Maximum Ratings Go
  • Added note of VLO clock frequency shift in LPM3 and LPM4 mode in Section 8.12.3.4, Internal Very-Low-Power Low-Frequency Oscillator (VLO) Go
  • Changed from RI to RI,MUX in Section 8.12.7.1, ADC, Power Supply and Input Range Conditions Go
  • Added RI,Misc TYP value 34kΩ in Section 8.12.7.1, ADC, Power Supply and Input Range Conditions Go
  • Removed ADCDIV from the conversion time formula because ADCCLK is after division in Section 8.12.7.2, ADC, 10-Bit Timing Parameters Go
  • Added formula for RI calculation in Section 8.12.7.2, ADC, 10-Bit Timing Parameters Go
  • Remove description of "±3°C" in table note that starts "The device descriptor structure ..." of Section 8.12.7.3, ADC, 10-Bit Linearity Parameters Go
  • Add "10b" for ADCSSEL bit in Table 9-6, Clock Distribution Go
  • Added "Clock Distribution Block Diagram" in Section 9.9.2, Clock System (CS) and Clock Distribution Go
  • Corrected bitfield from IRDSEL to IRDSSEL in Section 9.9.8, Timers (Timer0_A3, Timer1_A3), in the description that starts "The interconnection of Timer0_A3 and ..."Go
  • Corrected the ADCINCHx column heading in Table 9-12, ADC Channel Connections Go
  • Added word "Sensor" in Table 9-27, Device Descriptors Go
  • Added word "Sensor" in Table 9-27, Device Descriptors Go

Changes from revision B to revision C

Changes from August 15, 2015 to August 29, 2018

Changes from revision A to revision B

Changes from December 20, 2014 to August 14, 2015

  • 将特性“待机模式”电流消耗从 770nA 更改为 1µAGo
  • Added Section 8.2, ESD Ratings Go
  • Added ILPM3.5, LCD, CP TYP values at –40°C (0.90 µA) and at 85°C (1.27 µA)Go
  • Added the paragraph that starts "The graphs in this section..."Go
  • Changed all graphs in Section 8.9, Typical Characteristics, Low-Power Mode Supply Currents, for new measurements Go
  • Added VREF, 1.2V parameter to Section 8.12.1.1, PMM, SVS and BOR Go
  • Changed tSTE,LEAD MIN value at 2 V from 40 ns to 50 nsGo
  • Changed tSTE,LEAD MIN value at 3 V from 24 ns to 45 nsGo
  • Changed tVALID,SO MAX value at 2 V from 55 ns to 65 nsGo
  • Changed tVALID,SO MAX value at 3 V from 30 ns to 40 nsGo
  • Changed fADCOSC TYP value from 4.5 MHz to 5.0 MHzGo
  • In Table 9-1, Operating Modes, changed the entry for "Power Consumption at 25°C, 3 V" in AM from 100 µA/MHz to 126 µA/MHzGo
  • In Table 9-1, Operating Modes, added "with RTC only" to the entry for "Power Consumption at 25°C, 3 V" in LPM3.5Go
  • In Table 9-2, Interrupt Sources, Flags, and Vectors, removed "FRAM access time error" (ACCTEIFG) from the "System NMI" row Go
  • In Table 9-8, System Module Interrupt Vector Registers, changed the interrupt event in the SYSSNIV row with a VALUE of 06h from "ACCTEIFG access time error" to "Reserved"Go
  • In Table 9-27, Device Descriptors, added note to "CRC value"Go

Changes from initial release to revision A

Changes from October 3, 2014 to December 19, 2014

  • Moved Tstg to Absolute Maximum Ratings table and added note (3)Go
  • Changed link to BSL user's guide in Section 9.4 Go
  • Added note (1) to Table 9-6 Go
  • Changed the values of ADC Calibration Tag and ADC Calibration Length in the ADC Calibration rowGo
  • Added Calibration Tag, Calibration Length, and 1.5-V Reference in the Reference and DCO Calibration rowGo
  • Added row for BSL memory to Table 9-28 Go