ZHCSJT3B May   2019  – August 2020 LP5009 , LP5012

PRODUCTION DATA  

  1. 特性
  2. 应用
  3. 说明
  4. Revision History
  5. Description (continued)
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Characteristics
    7. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 PWM Control for Each Channel
        1. 8.3.1.1 Independent Color Mixing Per RGB LED Module
        2. 8.3.1.2 Independent Intensity Control Per RGB LED Module
          1. 8.3.1.2.1 Intensity-Control Register Configuration
          2. 8.3.1.2.2 Logarithmic- or Linear-Scale Intensity Control
        3. 8.3.1.3 12-Bit, 29-kHz PWM Generator Per Channel
          1. 8.3.1.3.1 PWM Generator
        4. 8.3.1.4 PWM Phase-Shifting
      2. 8.3.2 LED Bank Control
      3. 8.3.3 Current Range Setting
      4. 8.3.4 Automatic Power-Save Mode
      5. 8.3.5 Protection Features
        1. 8.3.5.1 Thermal Shutdown
        2. 8.3.5.2 UVLO
    4. 8.4 Device Functional Modes
    5. 8.5 Programming
      1. 8.5.1 I2C Interface
        1. 8.5.1.1 Data Validity
        2. 8.5.1.2 Start and Stop Conditions
        3. 8.5.1.3 Transferring Data
        4. 8.5.1.4 I2C Slave Addressing
        5. 8.5.1.5 Control-Register Write Cycle
        6. 8.5.1.6 Control-Register Read Cycle
        7. 8.5.1.7 Auto-Increment Feature
    6. 8.6 Register Maps
      1.      45
      2. 8.6.1  DEVICE_CONFIG0 (Address = 0h) [reset = 0h]
      3. 8.6.2  DEVICE_CONFIG1 (Address = 1h) [reset = 3Ch]
      4. 8.6.3  LED_CONFIG0 (Address = 2h) [reset = 00h]
      5. 8.6.4  BANK_BRIGHTNESS (Address = 3h) [reset = FFh]
      6. 8.6.5  BANK_A_COLOR (Address = 4h) [reset = 00h]
      7. 8.6.6  BANK_B_COLOR (Address = 5h) [reset = 00h]
      8. 8.6.7  BANK_C_COLOR (Address = 6h) [reset = 00h]
      9. 8.6.8  LED0_BRIGHTNESS (Address = 7h) [reset = FFh]
      10. 8.6.9  LED1_BRIGHTNESS (Address = 8h) [reset = FFh]
      11. 8.6.10 LED2_BRIGHTNESS (Address = 9h) [reset = FFh]
      12. 8.6.11 LED3_BRIGHTNESS (Address = 0Ah) [reset = FFh]
      13. 8.6.12 OUT0_COLOR (Address = 0Bh) [reset = 00h]
      14. 8.6.13 OUT1_COLOR (Address = 0Ch) [reset = 00h]
      15. 8.6.14 OUT2_COLOR (Address = 0Dh) [reset = 00h]
      16. 8.6.15 OUT3_COLOR (Address = 0Eh) [reset = 00h]
      17. 8.6.16 OUT4_COLOR (Address = 0Fh) [reset = 00h]
      18. 8.6.17 OUT5_COLOR (Address = 10h) [reset = 00h]
      19. 8.6.18 OUT6_COLOR (Address = 11h) [reset = 00h]
      20. 8.6.19 OUT7_COLOR (Address = 12h) [reset = 00h]
      21. 8.6.20 OUT8_COLOR (Address = 13h) [reset = 00h]
      22. 8.6.21 OUT9_COLOR (Address = 14h) [reset = 00h]
      23. 8.6.22 OUT10_COLOR (Address = 15h) [reset = 00h]
      24. 8.6.23 OUT11_COLOR (Address = 16h) [reset = 00h]
      25. 8.6.24 RESET (Address = 17h) [reset = 00h]
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Examples
  12. 12Device and Documentation Support
    1. 12.1 Related Links
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 支持资源
    4. 12.4 Trademarks
    5. 12.5 静电放电警告
    6. 12.6 术语表
  13. 13Mechanical, Packaging, and Orderable Information

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Layout Guidelines

To prevent thermal shutdown, the junction temperature, TJ, must be less than T(TSD). If the voltage drop across the output channels is high, the device power dissipation can be large. The LP50xx device has very good thermal performance because of the thermal pad design; however, the PCB layout is also very important to ensure that the device has good thermal performance. Good PCB design can optimize heat transfer, which is essential for the long-term reliability of the device.

Use the following guidelines when designing the device layout:

  • Place the CVCAP, CVCCand RIREF as close to the device as possible. Also, TI recommends putting the ground plane as Figure 11-1 and Figure 11-2.
  • Maximize the copper coverage on the PCB to increase the thermal conductivity of the board. The major heat flow path from the package to the ambient is through copper on the PCB. Maximum copper density is extremely important when no heat sinks are attached to the PCB on the other side from the package.
  • Add as many thermal vias as possible directly under the package ground pad to optimize the thermal conductivity of the board.
  • Use either plated-shut or plugged and capped vias for all the thermal vias on both sides of the board to prevent solder voids. To ensure reliability and performance, the solder coverage must be at least 85%.