ZHCSGY9B July   2017  – March 2018 LMS3655

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      典型应用电路
      2.      LMS3655 效率：输出电压 = 5V
  4. 4 修订历史记录
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Thermal Information (for Device Mounted on PCB)
    6. 7.6 Electrical Characteristics
    7. 7.7 System Characteristics
    8. 7.8 Timing Requirements
    9. 7.9 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
      1. 8.2.1 Control Scheme
    3. 8.3 Feature Description
      1. 8.3.1 RESET Flag Output
      2. 8.3.2 Enable and Start-Up
      3. 8.3.3 Soft-Start Function
      4. 8.3.4 Current Limit
      5. 8.3.5 Hiccup Mode
      6. 8.3.6 Synchronizing Input
      7. 8.3.7 Undervoltage Lockout (UVLO) and Thermal Shutdown (TSD)
      8. 8.3.8 Input Supply Current
    4. 8.4 Device Functional Modes
      1. 8.4.1 AUTO Mode
      2. 8.4.2 FPWM Mode
      3. 8.4.3 Dropout
      4. 8.4.4 Spread-Spectrum Operation
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 General Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 External Components Selection
            1. 9.2.1.2.1.1 Input Capacitors
            2. 9.2.1.2.1.2 Output Inductors and Capacitors
              1. 9.2.1.2.1.2.1 Inductor Selection
              2. 9.2.1.2.1.2.2 Output Capacitor Selection
          2. 9.2.1.2.2 FB for Adjustable Output
          3. 9.2.1.2.3 VCC
          4. 9.2.1.2.4 BIAS
          5. 9.2.1.2.5 CBOOT
          6. 9.2.1.2.6 Maximum Ambient Temperature
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Adjustable 5-V Output
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
      3. 9.2.3 Adjustable 3.3-V Output
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
        3. 9.2.3.3 Application Curves
      4. 9.2.4 6-V Adjustable Output
        1. 9.2.4.1 Design Requirements
        2. 9.2.4.2 Detailed Design Procedure
        3. 9.2.4.3 Application Curves
    3. 9.3 Do's and Don't's
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 器件支持
      1. 12.1.1 第三方产品免责声明
    2. 12.2 文档支持
      1. 12.2.1 相关文档
    3. 12.3 接收文档更新通知
    4. 12.4 社区资源
    5. 12.5 商标
    6. 12.6 静电放电警告
    7. 12.7 Glossary
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

9.2.2.2 Detailed Design Procedure

  • BIAS is connected to the output. This example assumes that the load is connected to the output through long wires so a 3-Ω resistor is inserted to minimize risks of damage to the part during load shorts. In addition 0.1-µF capacitor is required close to the bias pin.
  • FB is connected to the output through a voltage divider in order to create a voltage of 1 V at the FB pin when the output is at 5 V. A 22-pF capacitance is added in parallel with the top feedback resistor in order to improve transient behavior. BIAS and FB are connected to the output through separate traces. This is important to reduce noise and achieve good performance. See Layout Guidelines for more details on the proper layout method.
  • SYNC is connected to ground through a pulldown resistor, and an external synchronization signal can be applied. The pulldown resistor ensures that the pin is not floating when the SYNC pin is not driven by any source.
  • EN is connected to VIN so the device operates as soon as the input voltage rises above the VIN-OPERATE threshold.
  • FPWM is connected to VIN. This causes the device to operate in FPWM mode. In this mode, the device remains in CCM operation regardless of the output current and is ensured to be within the boundaries set by FSW. To prevent frequency foldback behavior at low duty cycles, provide a 200-mA load. The drawback is that the efficiency is not optimized for light loads. SeeDevice Functional Modes for more details.
  • A 4.7-µF capacitor is connected between VCC and GND close to the VCC pin. This ensures stable operation of the internal LDO.
  • RESET is biased to the output in this example. A pullup resistor is necessary. A 100-kΩ is selected for this application and is generally sufficient. The value can be selected to match the needs of the application but must not lead to excessive current into the RESET pin when RESET is in a low state. ConsultAbsolute Maximum Ratings for the maximum current allowed. In addition, a low pullup resistor could lead to an incorrect logic level due to the value of RRESET. Consult Electrical Characteristics for details on the RESET pin.
  • Input capacitor selection is detailed in Input Capacitors. It is important to connect small high-frequency capacitors CIN_HF1 and CIN_HF2 as close to both inputs PVIN1 and PVIN2 as possible.
  • Output capacitor selection is detailed inOutput Capacitor Selection.
  • Inductor selection is detailed in Inductor Selection. In general, a 10-µH inductor is recommended for the nominal adjustable output range of 3.3 V to 5 V. The inductance can vary with the output voltage due to ripple and current limit requirements.