ZHCSH74B december 2017 – august 2023 LMK61E07
PRODUCTION DATA
The 12-bit N integer divider value for PLL is set by the PLL_NDIV_BY1 and PLL_NDIV_BY0 registers.
BIT NO. | FIELD | TYPE | DEFAULT | EEPROM | DESCRIPTION |
---|---|---|---|---|---|
[7:4] | RESERVED | - | - | N | Reserved. |
[3:0] | PLL_NDIV[11:8] | RW | 0x0 | Y | PLL N Divider Byte 1. PLL Integer N Divider
bits [11:8]. |