ZHCSH74B december 2017 – august 2023 LMK61E07
PRODUCTION DATA
The PLL_FRACNUM_BY0 register is described in the following table.
BIT NO. | FIELD | TYPE | DEFAULT | EEPROM | DESCRIPTION |
---|---|---|---|---|---|
[7:0] | PLL_NUM[7:0] | RW | 0x1F | Y | PLL Fractional Divider Numerator Byte 0. Bits [7:0]. When
using DCXO mode, the fractional numerator bits in R27, R28, and R29 should be
written in that order (MSB first and LSB last) to avoid intermediate frequency
jumps. |