ZHCSFX5C December   2016  – December 2017 LMK60E0-156M , LMK60E0-212M , LMK60E2-100M , LMK60E2-125M , LMK60E2-156M , LMK60I2-100M , LMK60I2-322M

PRODUCTION DATA.  

  1. 特性
  2. 应用
  3. 说明
    1.     Device Images
      1.      引脚分配
  4. 修订历史记录
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - Power Supply
    6. 6.6  LVPECL Output Characteristics
    7. 6.7  LVDS Output Characteristics
    8. 6.8  HCSL Output Characteristics
    9. 6.9  OE Input Characteristics
    10. 6.10 Frequency Tolerance Characteristics
    11. 6.11 Power-On/Reset Characteristics (VDD)
    12. 6.12 PSRR Characteristics
    13. 6.13 PLL Clock Output Jitter Characteristics
    14. 6.14 Additional Reliability and Qualification
  7. Parameter Measurement Information
    1. 7.1 Device Output Configurations
  8. Power Supply Recommendations
  9. Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1 Ensuring Thermal Reliability
      2. 9.1.2 Best Practices for Signal Integrity
      3. 9.1.3 Recommended Solder Reflow Profile
  10. 10器件和文档支持
    1. 10.1 接收文档更新通知
    2. 10.2 社区资源
    3. 10.3 商标
    4. 10.4 静电放电警告
    5. 10.5 Glossary
  11. 11机械、封装和可订购信息

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • SIA|6
订购信息

Best Practices for Signal Integrity

For best electrical performance and signal integrity of entire system with LMK60EX, TI recommends routing vias into decoupling capacitors and then into the LMK60EX. TI also recommends increasing the via count and width of the traces wherever possible. These steps ensure lowest impedance and shortest path for high frequency current flow. Figure 9 shows the layout recommendation for LMK60EX.

LMK60E2-100M LMK60E2-125M LMK60E2-156M LMK60E0-156M LMK60E0-212M LMK60I2-100M LMK60I2-322M layout_example_snas687.pngFigure 9. LMK60EX Layout Recommendation for Power Supply and Ground