ZHCSCZ6C December   2013  – July 2021 LMK00338

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Differential Voltage Measurement Terminology
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Crystal Power Dissipation vs. RLIM
      2. 8.3.2 Clock Inputs
      3. 8.3.3 Clock Outputs
        1. 8.3.3.1 Reference Output
    4. 8.4 Device Functional Modes
      1. 8.4.1 VCC and VCCO Power Supplies
  9. 9 Power Supply Recommendations
    1. 9.1 Current Consumption and Power Dissipation Calculations
      1. 9.1.1 Power Dissipation Example: Worst-Case Dissipation
    2. 9.2 Power Supply Bypassing
      1. 9.2.1 Power Supply Ripple Rejection
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Management
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 接收文档更新通知
    3. 11.3 支持资源
    4. 11.4 Trademarks
    5. 11.5 静电放电警告
    6. 11.6 术语表

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

4 Revision History

Changes from Revision B (June 2017) to Revision C (July 2021)

  • 将数据表标题从LMK00338 8 路输出差动时钟缓冲器和电平转换器 更改为：LMK00338 8 路输出 PCIe 第 1 代/第 2 代/第 3 代/第 4 代/第 5 代时钟缓冲器和电平转换器 Go
  • 更改了目标应用，方法为将附加应用添加到第二个和第三个要点，并且从第一个要点中删除高速和串行接口。Go
  • 在数据表中添加了 PCIe 第 5 代Go
  • Changed guarantee to ensure throughout.Go
  • Added PCIe 4.0 compliance dataGo
  • Added additive RMS phase jitter for PCIe 4.0 and PCIe 5.0 to the Electrical Characteristics tableGo
  • Removed the LVPECL Phase Noise at 100 MHz graph Go
  • Changed the third paragraph in Driving the Clock Inputs section to include CLKin* and LVCMOS text. Revised to better correspond with information in the Electrical Characteristics tableGo
  • Changed the bypass cap text to signal attenuation text of the fourth paragraph in Driving the Clock Inputs section.Go
  • Changed the Single-Ended LVCMOS Input, DC Coupling with Common Mode Biasing image with revised graphic.Go

Changes from Revision A (October 2014) to Revision B (June 2017)

  • 已将整个数据表中的 CLKoutA_EN 和 CLKoutB_EN 引脚更改为 CLKoutA_EN 和 CLKoutB_EN Go

Changes from Revision * (December 2013) to Revision A (October 2014)

  • 添加、更新或重命名了以下各个部分：器件信息表、应用和实施；电源建议；布局；器件和文档支持；机械、封装和可订购信息 Go
  • Added PCIE Gen4 additive jitter to the Electrical Characteristics table Go
  • Changed 1 MHz to 12 kHz Go
  • Added Figure 10-1 Go