ZHCSHO1D November   2018  – January 2019 LMG1210

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      简化的典型应用
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
    8. 6.8 Timing Diagrams
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Bootstrap Diode Operation
      2. 7.3.2 LDO Operation
      3. 7.3.3 Dead Time Selection
      4. 7.3.4 Overtemperature Protection
      5. 7.3.5 High-Performance Level Shifter
      6. 7.3.6 Negative HS Voltage Handling
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Bypass Capacitor
        2. 8.2.2.2 Bootstrap Diode Selection
        3. 8.2.2.3 Handling Ground Bounce
        4. 8.2.2.4 Independent Input Mode
        5. 8.2.2.5 Computing Power Dissipation
      3. 8.2.3 Application Curves
    3. 8.3 Do's and Don'ts
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 文档支持
      1. 11.1.1 相关文档
    2. 11.2 接收文档更新通知
    3. 11.3 社区资源
    4. 11.4 商标
    5. 11.5 静电放电警告
    6. 11.6 术语表
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
  • RVR|19
散热焊盘机械数据 (封装 | 引脚)
订购信息

10.1 Layout Guidelines

The layout of the LMG1210 is critical for performance and functionality. The low inductance WQFN package helps mitigate many of the problems associated with board level parasitics, but take care with layout and placement with components to ensure proper operation. The following design rules are recommended.

  • Place LMG1210 as close to the GaN FETs as possible to minimize the length of high-current traces between the HO/LO and the Gate of the GaN FETs
  • Place bootstrap diode as close as possible to the LMG1210 to minimize the inductance of the BST to HB loop.
  • Place the bypass capacitors across VIN to VSS, VDD to VSS, and HB to HS as close to the LMG1210 pins as possible. The VDD to VSS cap is a higher priority than the VIN to VSS cap.
  • Separate power traces and signal traces, such as output and input signals, and minimize any overlaps between layers
  • Minimize capacitance from the high-side pins to the input pins to minimize noise injection.