ZHCSHU0C March   2018  – October 2021 LM51501-Q1

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Enable (EN Pin)
      2. 8.3.2  High Voltage VCC Regulator (PVCC, AVCC Pin)
      3. 8.3.3  Power-On Voltage Selection (VSET Pin)
      4. 8.3.4  Switching Frequency (RT Pin)
      5. 8.3.5  Clock Synchronization (SYNC Pin in SS Configuration)
      6. 8.3.6  Current Sense, Slope Compensation, and PWM (CS Pin)
      7. 8.3.7  Current Limit (CS Pin)
      8. 8.3.8  Feedback and Error Amplifier (COMP Pin)
      9. 8.3.9  Automatic Wake-Up and Standby
      10. 8.3.10 Boost Status Indicator (STATUS Pin)
      11. 8.3.11 Maximum Duty Cycle Limit and Minimum Input Supply Voltage
      12. 8.3.12 MOSFET Driver (LO Pin)
      13. 8.3.13 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown Mode
      2. 8.4.2 Standby Mode
      3. 8.4.3 Wake-Up Mode
        1. 8.4.3.1 Start-Stop Configuration (SS Configuration)
        2. 8.4.3.2 Emergency-Call Configuration (EC Configuration)
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Bypass Switch / Disconnection Switch Control
      2. 9.1.2 Loop Response
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Custom Design With WEBENCH® Tools
        2. 9.2.2.2  RSET Resistor
        3. 9.2.2.3  RT Resistor
        4. 9.2.2.4  Inductor Selection (LM)
        5. 9.2.2.5  Current Sense (RS)
        6. 9.2.2.6  Slope Compensation Ramp (RSL)
        7. 9.2.2.7  Output Capacitor (COUT)
        8. 9.2.2.8  Loop Compensation Component Selection and Maximum ESR
        9. 9.2.2.9  PVCC Capacitor, AVCC Capacitor, and AVCC Resistor
        10. 9.2.2.10 VOUT Filter (CVOUT, RVOUT)
        11. 9.2.2.11 Input Capacitor
        12. 9.2.2.12 MOSFET Selection
        13. 9.2.2.13 Diode Selection
        14. 9.2.2.14 Efficiency Estimation
      3. 9.2.3 Application Curves
    3. 9.3 System Examples
      1. 9.3.1 Lower Standby Threshold in SS Configuration
      2. 9.3.2 Dithering Using Dither Enabled Device
      3. 9.3.3 Clock Synchronization With LM5140
      4. 9.3.4 Dynamic Frequency Change
      5. 9.3.5 Dithering Using an External Clock
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 第三方产品免责声明
      2. 12.1.2 Development Support
        1. 12.1.2.1 Custom Design With WEBENCH® Tools
    2. 12.2 接收文档更新通知
    3. 12.3 支持资源
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 术语表
  13. 13Mechanical, Packaging, and Orderable Information

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • RUM|16
散热焊盘机械数据 (封装 | 引脚)
订购信息

8.3.6 Current Sense, Slope Compensation, and PWM (CS Pin)

The LM51501-Q1 features low-side current sense amplifier with a gain of 10, and provides an internal slope compensation ramp to prevent subharmonic oscillation at high duty cycle. The device generates the slope compensation ramp using a sawtooth current source with a slope of 30 µA × FSW (typical). This current flows through an internal 2-kΩ resistor and out of the CS pin. The slope compensation ramp is determined by the RT resistor and is 60 mV × FSW (typical) at the input of the current sense amplifier and 600 mV × FSW (typical) at the output of the current sense amplifier. The slope compensation ramp can be increased by adding an external slope resistor (RSL) between the sense resistor (RS) and the CS pin, but take extra care when using the RSL, because the peak current limit is affected by adding RSL. See tSection 8.3.7 for more detailed information.

GUID-FC13B8F8-1016-4DF6-BBE0-D72A8DCE1ADD-low.gifFigure 8-2 Current Sensing and Slope Compensation

According to peak current mode control theory, the slope of the compensation ramp must be greater than half of the sensed inductor current falling slope to prevent subharmonic oscillation at high duty cycle. Therefore, the minimum amount of slope compensation should satisfy the inequality in Equation 4.

Equation 4. GUID-2F2C2443-87F4-45CE-A72F-0586BBAEC390-low.gif

VF is a forward voltage drop of D1, the external diode. 1.2 is recommended as a margin to cover non-ideal factors.

If required, RSL can be added to increase the slope of the compensation ramp from half to 82% of the slope of the sensed inductor current during the falling slope. The typical RSL value is calculated using Equation 5. The maximum RSL value is 1 kΩ.

Equation 5. GUID-4C287C8F-7D9F-4DCE-879C-40B4EAEB01DC-low.gif

The PWM comparator in Figure 8-2 compares the sum of the sensed inductor current, the slope compensation ramp, and a 0.3-V (typical) internal COMP-to-PWM offset with the COMP pin voltage (VCOMP), and will terminate the present cycle if the sum is greater than VCOMP.