SNVS443C May   2006  – December 2016 LM3489 , LM3489-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings: LM3489
    3. 6.3 ESD Ratings: LM3489-Q1
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Electrical Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Hysteretic Control Circuit
        1. 7.3.1.1 Delay
      2. 7.3.2 Current Limit Operation
      3. 7.3.3 Start Up
      4. 7.3.4 External Sense Resistor
      5. 7.3.5 PGATE
      6. 7.3.6 Adjustable UVLO
    4. 7.4 Device Functional Mode
      1. 7.4.1 Device Enable and Shutdown
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Inductor Selection (L)
        2. 8.2.2.2 Output Capacitor Selection (COUT)
        3. 8.2.2.3 Input Capacitor Selection (CIN)
        4. 8.2.2.4 Programming the Current Limit (RADJ)
        5. 8.2.2.5 Catch Diode Selection (D1)
        6. 8.2.2.6 P-Channel MOSFET Selection (Q1)
        7. 8.2.2.7 Interfacing With the Enable Pin
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Related Links
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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机械数据 (封装 | 引脚)
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订购信息

5 Pin Configuration and Functions

DGK Package
8-Pin VSSOP
Top View

Pin Functions

PIN I/O DESCRIPTION
NO. NAME
1 ISENSE I The current sense input pin. This pin must be connected to the PFET drain terminal directly or through a series resistor up to 600 Ω for 28 V > VIN > 35 V.
2 GND — Signal ground
3 EN I Enable pin. Connect EN pin to ground to shutdown the part or float to enable operation (Internally pulled high). This pin can also be used to perform UVLO function.
4 FB I The feedback input. Connect the FB to a resistor voltage divider between the output and GND for an adjustable output voltage.
5 ADJ I Current limit threshold adjustment. Connected to an internal 5.5-µA current source. A resistor is connected between this pin and VIN. The voltage across this resistor is compared with the ISENSE pin voltage to determine if an overcurrent condition has occurred.
6 PGND — Power ground
7 PGATE O Gate drive output for the external PFET. PGATE swings between VIN and VIN 5-V.
8 VIN I Power supply input pin