10.1 Layout Guidelines

The PCB layout is very important in all switching regulator designs. Poor layout can cause switching noise into the feedback signal and generate EMI problems. For minimal inductance, the wires indicated by heavy lines in schematic diagram must be as wide and short as possible. Keep the ground pin of the input capacitor as close as possible to the anode of the catch diode. This path carries a large AC current. The switching node, the node with the diode cathode, inductor and FET drain must be kept short. This node is one of the main sources for radiated EMI since it sees a large AC voltage at the switching frequency. It is always a good practice to use a ground plane in the design, particularly for high-current applications.

The two ground pins, PGND and GND, must be connected by as short a trace as possible. They can be connected underneath the device. These pins are resistively connected internally by approximately 50 Ω. The ground pins must be tied to the ground plane, or to a large ground trace in close proximity to both the FB divider and C_OUT grounds.

The gate pin of the external PFET must be placed close to the PGATE pin. However, if a very small FET is used, a resistor may be required between PGATE pin and the gate of the PFET to reduce high-frequency ringing. Because this resistor will slow down the PFET’s rise time, the current limit blanking time must be taken into consideration (see Current Limit Operation). The feedback voltage signal line can be sensitive to noise. Avoid inductive coupling with the inductor or the switching node. The FB trace must be kept away from those areas. Also, the orientation of the inductor can contribute un-wanted noise coupling to the FB path. If noise problems are observed it may be worth trying a different orientation of the inductor and select the best for final component placement.

10.2 Layout Examples

SPACE

Figure 30. LM3489 EVM PCB Top Layer Layout

Figure 31. LM3489 EVM PCB Bottom Layer Layout