7.3.1 Buck Regulators Description

The LM10504 incorporates three high-efficiency synchronous switching buck regulators that deliver various voltages from a single DC input voltage. They include many advanced features to achieve excellent voltage regulation, high efficiency, and fast transient response time. The bucks feature voltage mode architecture with synchronous rectification.

Each of the switching regulators is specially designed for high-efficiency operation throughout the load range. With a 2MHz typical switching frequency, the external L-C filter can be small and still provide very low output voltage ripple. The bucks are internally compensated to be stable with the recommended external inductors and capacitors as detailed in the application diagram. Synchronous rectification yields high efficiency for low voltage and high output currents.

All bucks can operate up to a 100% duty cycle allowing for the lowest possible input voltage that still maintains the regulation of the output. The lowest input to output dropout voltage is achieved by keeping the PMOS switch on.

Additional features include soft start, undervoltage lockout, bypass, and current and thermal overload protection. To reduce the input current ripple, the device employs a control circuit that operates the 3 bucks at 120° phase. These bucks are nearly identical in performance and mode of operation. They can operate in FPWM (forced PWM) or automatic mode (PWM/PFM).

7.3.2 PWM Operation

During PWM operation the converter operates as a voltage-mode controller with input voltage feedforward. This allows the converter to achieve excellent load and line regulation. The DC gain of the power stage is proportional to the input voltage. To eliminate this dependence, a feedforward voltage inversely proportional to the input voltage is introduced.

In forced PWM mode the bucks always operate in PWM mode regardless of the output current.

In automatic mode, if the output current is less than 70 mA (typical), the bucks automatically transition into Pulse Frequency Modulation (PFM) operation to reduce the current consumption. At higher than 100 mA (typical), they operate in PWM mode. This increases the efficiency at lower output currents. The 30-mA (typical) hysteresis is designed in for stable mode transition.

While in PWM mode, the output voltage is regulated by switching at a constant frequency and then modulating the energy per cycle to control power to the load. At the beginning of each clock cycle the PFET switch is turned on, and the inductor current ramps up until the comparator trips and the control logic turns off the switch. The current limit comparator can also turn off the switch in case the current limit of the PFET is exceeded. In this case the NFET switch is turned on and the inductor current ramps down. The next cycle is initiated by the clock turning off the NFET and turning on the PFET.

Figure 20. PFM vs PWM Operation

7.3.3 PFM Operation

At very light loads, Bucks 1, 2, and 3 enter PFM mode and operate with reduced switching frequency and supply current to maintain high efficiency.

Bucks 1, 2, and 3 automatically transitions into PFM mode when either of two conditions occurs for a duration of 32 or more clock cycles:

1. The inductor current becomes discontinuous
2. The peak PMOS switch current drops below the I_MODE level.

During PFM operation, the converter positions the output voltage slightly higher than the nominal output voltage during PWM operation, allowing additional headroom for voltage drop during a load transient from light to heavy load. The PFM comparators sense the output voltage through the feedback pin and control the switching of the output FETs such that the output voltage ramps between 0.8% and 1.6% (typical) above the nominal PWM output voltage. If the output voltage is below the ‘high’ PFM comparator threshold, the PMOS power switch is turned on. It remains on until the output voltage exceeds the ‘high’ PFM threshold or the peak current exceeds the I_PFM level set for PFM mode.

Once the PMOS power switch is turned off, the NMOS power switch is turned on until the inductor current ramps to zero. When the NMOS zero-current condition is detected, the NMOS power switch is turned off. If the output voltage is below the ‘high’ PFM comparator threshold (see Figure 20), the PMOS switch is again turned on and the cycle is repeated until the output reaches the desired level. Once the output reaches the high PFM threshold, the NMOS switch is turned on briefly to ramp the inductor current to zero and then both output switches are turned off and the part enters an extremely low power mode. Quiescent supply current during this idle mode is less than 100 µA, which allows the part to achieve high efficiencies under extremely light load conditions. When the output drops below the ‘low’ PFM threshold, the cycle repeats to restore the output voltage to approximately 1.6% above the nominal PWM output voltage.

If the load current must increase during PFM mode causing the output voltage to fall below the ‘low2’ PFM threshold, the part automatically transitions into fixed-frequency PWM mode.

7.3.4 Soft Start

Each of the buck converters has an internal soft-start circuit that limits the in-rush current during start-up. This allows the converters to gradually reach the steady-state operating point, thus reducing start-up stresses and surges. During start-up, the switch current limit is increased in steps.

For Bucks 1, 2, and 3 the soft start is implemented by increasing the switch current limit in steps that are gradually set higher. The start-up time depends on the output capacitor size, load current, and output voltage. Typical start-up time with the recommended output capacitor of 10 µF is 0.2 to 1ms. It is expected that in the final application the load current condition is more likely in the lower load current range during start-up.

7.3.5 Current Limiting

A current limit feature protects the device and any external components during overload conditions. In PWM mode the current limiting is implemented by using an internal comparator that trips at current levels according to the buck capability. If the output is shorted to ground the device enters a timed current limit mode where the NFET is turned on for a longer duration until the inductor current falls below a low threshold, ensuring inductor current has more time to decay, thereby preventing runaway.

7.3.6 Internal Synchronous Rectification

While in PWM mode, the bucks use an internal NFET as a synchronous rectifier to reduce the rectifier forward voltage drop and the associated power loss. Synchronous rectification provides a significant improvement in efficiency whenever the output voltage is relatively low compared to the voltage drop across an ordinary rectifier diode.

7.3.7 Bypass-FET Operation on Buck 1 and Buck 2

There is an additional bypass FET used on Buck 1. The FET is connected in parallel to high-side FET and inductor. Buck 2 has no extra bypass FET; it uses high-side FET (PFET) for bypass operation. If Buck 1 input voltage is greater than 3.5 V (2.6 V for Buck 2), the bypass function is disabled. The determination of whether or not the Buck regulators are in bypass mode or standard switching regulation is constantly monitored while the regulators are enabled. If at any time the input voltage goes above 3.5 V (2.6 V for Buck 2) while in bypass mode, the regulators transitions to normal operation.

When the bypass mode is enabled, the output voltage of the buck that is in bypass mode is not regulated, but instead, the output voltage follows the input voltage minus the voltage drop seen across the FET and DCR of the inductor. The voltage drop is a direct result of the current flowing across those resistive elements. When Buck 1 transitions into bypass mode, there is an extra FET used in parallel along with the high-side FET for transmission of the current to the load. This added FET helps reduce the resistance seen by the load and decrease the voltage drop. For Buck 2, the bypass function uses the same high-side FET.

Figure 21. Bypass Operations for Buck 1 and Buck 2

7.3.8 Low Dropout Operation

The device can operate at 100% duty cycle (no switching; PMOS switch completely on) for low dropout support. In this way, the output voltage is controlled down to the lowest possible input voltage. When the device operates near 100% duty cycle, output voltage ripple is approximately 25 mV.

The minimum input voltage needed to support the output voltage is calculated with Equation 1.

7.3.9 Out of Regulation

When any of the Buck outputs are taken out of regulation (below 85% of the output level), the device starts a shutdown sequence and all other outputs switch off normally. The device restarts when the forced out-of-regulation condition is removed.

7.4.1 Start-Up Sequence

The start-up mode of the LM10504 depends on the input voltage. Once VIN reaches the UVLO threshold, there is a 15-ms delay before the LM10504 determines how to set up the buck regulators. If V_IN is below 3.6 V, then Buck 1 and Buck 2 are in bypass mode; see Bypass-FET Operation on Buck 1 and Buck 2 for functionality description. If the VIN voltage is greater than 3.6 V, the bucks start up as standard regulators. The 3 buck regulators are staggered during start-up to avoid large inrush currents. There is a fixed delay of 2 ms between the start-up of each regulator.

The start-up sequence is:

1. 15 msec (±30%) delay after V_IN above UVLO
2. LDO → 3.2 V
3. 2-ms delay
4. Buck 1 → 3 V
5. 2-ms delay
6. Buck 2 → 3 V or if Vselect_B2 = Low → 1.8 V
7. 2-ms delay
8. Buck 3 → 1.2 V or if Vselect_B3 = Low → 1 V

Figure 22. Operating Modes

7.4.2 Power-On Default and Device Enable

The device is always enabled and the LDO is always on, unless outside of operating voltage range. There is no LM10504 Enable pin. Once V_IN reaches a minimum required input voltage, the power-up sequence is started automatically and the start-up sequence is initiated. Once the device is started, the output voltage of the Bucks 1 and 2 can be individually disabled by accessing their corresponding BKEN register bits (BUCK CONTROL).

7.4.3 Reset Pin Function

The RESET pin is internally pulled high. If the RESET pin is pulled low, the device performs a complete reset of all the registers to their default states. This means that all of the voltage settings on the regulators go back to their default states.

7.4.4 DevSLP Function

The device can be placed into sleep (DevSLP) mode. There are two ways for doing that:

1. DevSLP pin
2. Programming through the SPI

Bucks 1 and 2 are ramped down when the disable signal is given. Buck 1 starts ramping 2 ms after Buck 2 has started ramping.

To enter the DevSLP sequence:

1. Buck 3 → PSML (Programmable DevSLP Mode Level)
2. 2-ms delay
3. Buck 2 → Disabled
4. 2-ms delay
5. Buck 1 → Disabled

7.4.5 Vselect_B2, Vselect_B3 Function

The Vselect_B2/3 pins are digital pins which control alternate voltage selections of Buck 2 and Buck 3, respectively. Vselect_B2 has an internal pulldown which defaults to a 1.8-V output voltage selection for Buck 2. Alternatively, if Vselect_B2 is driven high, an output voltage of 3 V is selected. Vselect_B3 has an internal pullup which defaults to a 1.2-V output voltage selection for Buck 3. Alternatively, if Vselect_B3 is driven low, an output voltage of 1 V is selected. The pullup resistor is connected to the main input voltage. Transitions of the pins does not affect the output voltage, the state is only checked during start-up.

7.4.6 Undervoltage Lockout (UVLO)

The V_IN voltage is monitored for a supply under voltage condition, for which the operation of the device can not be ensured. The part automatically disables Buck 3. To prevent unstable operation, the undervoltage lockout (UVLO) has a hysteresis window of about 300 mV. An UVLO forces the device into the reset state, all internal registers are reset. Once the supply voltage is above the UVLO hysteresis, the device initiates a power-up sequence and then enter the active state.

Buck 1 and Buck 2 remain in bypass mode after V_IN passes the UVLO until V_IN reaches approximately 1.9 V. When Buck 2 is set to 1.8 V, the voltage jumps from 1.8 V to V_{UVLO_FALLING}, and then follow V_IN.

The LDO and the comparator remains functional past the UVLO threshold until V_IN reaches approximately 2.25 V.

7.4.7 Overvoltage Lockout (OVLO)

The V_IN voltage is monitored for a supply overvoltage condition, for which the operation of the device cannot be ensured. The purpose of overvoltage lockout (OVLO) is to protect the part and all other consumers connected to the PMU outputs from any damage and malfunction. Once V_IN rises over 5.64 V all the Bucks, and LDO is disabled automatically. To prevent unstable operation, the OVLO has a hysteresis window of about 100 mV. An OVLO forces the device into the reset state; all internal registers are reset. Once the supply voltage is below the OVLO hysteresis, the device initiates a power-up sequence, and then enter the active state. Operating maximum input voltage at which parameters are ensured is 5.5 V. Absolute maximum of the device is 6 V.

7.4.8 Device Status, Interrupt Enable

The LM10504 has 2 interrupt registers, INTERRUPT ENABLE and INTERRUPT STATUS. These registers can be read through the serial interface. The interrupts are not latched to the register, always represents the current state, and does not clear on read.

If interrupt condition is detected, then corresponding bit in the INTERRUPT STATUS register (0x0D) is set to '1', and Interrupt output is asserted. There are 5 interrupt generating conditions:

• Buck 3 output is over flag level (90% when rising, 85% when falling)
• Buck 2 output is over flag level (90% when rising, 85% when falling)
• Buck 1 output is over flag level (90% when rising, 85% when falling)
• LDO is over flag level (90% when rising, 85% when falling
• Comparator input voltage crosses over selected threshold

Reading the interrupt register does not release interrupt output. Interrupt generation conditions can be individually enabled or disabled by writing respective bits in INTERRUPT ENABLE register (0x0C) to 1 or 0.

7.4.9 Thermal Shutdown (TSD)

The temperature of the silicon die is monitored for an overtemperature condition, for which the operation of the device can not be ensured. The part is automatically disabled if the temperature is too high (>140°C). The thermal shutdown (TSD) forces the device into the reset state. In reset, all circuitry is disabled. To prevent unstable operation, the TSD has a hysteresis window of about 20°C. Once the temperature has decreased below the TSD hysteresis, the device initiates a power-up sequence and then enter the active state. In the active state, the part starts up as if for the first time, all registers are in their default state.

7.4.10 Comparator

The comparator on the LM10504 takes its inputs from the VCOMP pin and an internal threshold level which is programmed by the user. The threshold level is programmable between 2 and 4 V with a step of 31 mV and a default comp code of 0x19. The output of the comparator is the Interrupt pin. Its polarity can be changed using Register 0x0E bit 0. If Interrupt_polarity = 0 → Active low (default) is selected, then the output is low if V_COMP value is greater than the threshold level. The output is high if the V_COMP value is less than the threshold level. If Interrupt_polarity = 1 → Active high is selected then the output is high if V_COMP value is greater than the threshold level. The output is low if the V_COMP value is less than the threshold level. There is some hysteresis when V_COMP transitions from high to low, typically 60 mV. There is a control bit in register 0x0B, comparator control, that can double the hysteresis value.

Table 1. Registers Configurable Through SPI Interface