SNOSB66B August   2011  – November 2014 EMB1412

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Handling Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
  7. Detailed Description
    1. 7.1 Overview
  8. Layout
    1. 8.1 Layout Guidelines
    2. 8.2 Thermal Performance
  9. Device and Documentation Support
    1. 9.1 Trademarks
    2. 9.2 Electrostatic Discharge Caution
    3. 9.3 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

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订购信息

8 Layout

8.1 Layout Guidelines

Attention must be given to board layout when using EMB1412. Some important considerations include:

  1. A Low ESR/ESL capacitor must be connected close to the IC and between the VCC and VEE pins to support high peak currents being drawn from VCC during turn-on of the MOSFET.
  2. Proper grounding is crucial. The driver needs a very low impedance path for current return to ground avoiding inductive loops. Two paths for returning current to ground are a) between EMB1412 IN_REF pin and the ground of the circuit that controls the driver inputs and b) between EMB1412 VEE pin and the source of the power MOSFET being driven. Both paths should be as short as possible to reduce inductance and be as wide as possible to reduce resistance. These ground paths should be distinctly separate to avoid coupling between the high current output paths and the logic signals that drive the EMB1412. With rise and fall times in the range of 10 to 30 nsec, care is required to minimize the lengths of current carrying conductors to reduce their inductance and EMI from the high di/dt transients generated when driving large capacitive loads.
  3. If either channel is not being used, the respective input pin (IN or INB) should be connected to either VEE or VCC to avoid spurious output signals.

8.2 Thermal Performance

The primary goal of the thermal management is to maintain the integrated circuit (IC) junction temperature (TJ) below a specified limit to ensure reliable long term operation. The maximum TJ of IC components should be estimated in worst case operating conditions. The junction temperature can be calculated based on the power dissipated on the IC and the junction to ambient thermal resistance RθJA for the IC package in the application board and environment. The RθJA is not a given constant for the package and depends on the PCB design and the operating environment.