SNLS321C May   2010  – May 2016 DS92LV2421 , DS92LV2422

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - Serializer DC
    6. 6.6  Electrical Characteristics - Deserializer DC
    7. 6.7  Electrical Characteristics - DC and AC Serial Control Bus
    8. 6.8  Timing Requirements - DC and AC Serial Control Bus
    9. 6.9  Timing Requirements - Serializer for CLKIN
    10. 6.10 Timing Requirements - Serial Control Bus
    11. 6.11 Switching Characteristics - Serializer
    12. 6.12 Switching Characteristics - Deserializer
    13. 6.13 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Data Transfer
      2. 7.3.2 Video Control Signal Filter - Serializer and Deserializer
      3. 7.3.3 Serializer Functional Description
        1. 7.3.3.1 EMI Reduction Features
          1. 7.3.3.1.1 Data Randomization and Scrambling
          2. 7.3.3.1.2 Serializer Spread Spectrum Compatibility
        2. 7.3.3.2 Signal Quality Enhancers
          1. 7.3.3.2.1 Serializer VOD Select (VODSEL)
          2. 7.3.3.2.2 Serializer De-Emphasis (De-Emph)
        3. 7.3.3.3 Power-Saving Features
          1. 7.3.3.3.1 Serializer Power-Down Feature (PDB)
          2. 7.3.3.3.2 Serializer Stop Clock Feature
          3. 7.3.3.3.3 1.8-V or 3.3-V VDDIO Operation
          4. 7.3.3.3.4 Deserializer Power-Down Feature (PDB)
          5. 7.3.3.3.5 Deserializer Stop Stream SLEEP Feature
        4. 7.3.3.4 Serializer Pixel Clock Edge Select (RFB)
        5. 7.3.3.5 Optional Serial Bus Control
        6. 7.3.3.6 Optional BIST Mode
      4. 7.3.4 Deserializer Functional Description
        1. 7.3.4.1  Signal Quality Enhancers
          1. 7.3.4.1.1 Deserializer Input Equalizer Gain (EQ)
        2. 7.3.4.2  EMI Reduction Features
          1. 7.3.4.2.1 Deserializer Output Slew Rate Select (OS_CLKOUT/OS_DATA)
          2. 7.3.4.2.2 Deserializer Common-Mode Filter Pin (CMF) (Optional)
          3. 7.3.4.2.3 Deserializer SSCG Generation (Optional)
          4. 7.3.4.2.4 1.8-V or 3.3-V VDDIO Operation
        3. 7.3.4.3  Deserializer Clock-Data Recovery Status Flag (LOCK) And Output State Select (OSS_SEL)
        4. 7.3.4.4  Deserializer Oscillator Output (Optional)
        5. 7.3.4.5  Deserializer OP_LOW (Optional)
        6. 7.3.4.6  Deserializer Clock Edge Select (RFB)
        7. 7.3.4.7  Deserializer Control Signal Filter (Optional)
        8. 7.3.4.8  Deserializer Low Frequency Optimization (LF_Mode)
        9. 7.3.4.9  Deserializer Map Select
        10. 7.3.4.10 Deserializer Strap Input Pins
        11. 7.3.4.11 Optional Serial Bus Control
        12. 7.3.4.12 Optional BIST Mode
      5. 7.3.5 Built-In Self Test (BIST)
        1. 7.3.5.1 Sample BIST Sequence
        2. 7.3.5.2 BER Calculations
      6. 7.3.6 Optional Serial Bus Control
    4. 7.4 Device Functional Modes
      1. 7.4.1 Serializer and Deserializer Operating Modes and Reverse Compatibility (CONFIG[1:0])
    5. 7.5 Register Maps
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Display Application
      2. 8.1.2 Live Link Insertion
      3. 8.1.3 Alternate Color / Data Mapping
    2. 8.2 Typical Applications
      1. 8.2.1 DS92LV2421 Typical Connection
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
      2. 8.2.2 DS92LV2422 Typical Connection
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
  9. Power Supply Recommendations
    1. 9.1 Power-Up Requirements and PDB Pin
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 WQFN (LLP) Stencil Guidelines
      2. 10.1.2 Transmission Media
      3. 10.1.3 LVDS Interconnect Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Related Links
    4. 11.4 Community Resource
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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7 Detailed Description

7.1 Overview

The DS92LV242x chipset transmits and receives 24 bits of data and 3 control signals over a single serial CML pair operating at 280 Mbps to 2.1 Gbps. The serial stream also contains an embedded clock, video control signals, and the DC-balance information which enhances signal quality and supports AC coupling.

The deserializer can attain lock to a data stream without the use of a separate reference clock source, which greatly simplifies system complexity and overall cost. The deserializer also synchronizes to the serializer regardless of the data pattern, delivering true automatic plug and lock performance. It can lock to the incoming serial stream without the need of special training patterns or sync characters. The deserializer recovers the clock and data by extracting the embedded clock information, validating, and then deserializing the incoming data stream, providing a parallel LVCMOS video bus to the display, ASIC, or FPGA.

The DS92LV242x chipset can operate in 24-bit color depth (with DE, HS, VS encoded within the serial data stream). In 18-bit color applications, the three video control signals may be sent encoded within the serial bit stream (restrictions apply, see Video Control Signal Filter – Serializer and Deserializer) along with six additional general-purpose signals.

7.2 Functional Block Diagrams

DS92LV2421 DS92LV2422 30110128.gif Figure 21. DS92LV2421 – Serializer
DS92LV2421 DS92LV2422 30110129.gif Figure 22. DS92LV2422 – Deserializer

7.3 Feature Description

7.3.1 Data Transfer

The DS92LV242x chipset transmits and receives a pixel of data in the following format: C1 and C0 represent the embedded clock in the serial stream. C1 is always high and C0 is always low. The b[23:0] contains the scrambled LVCMOS data. DCB is the DC-Balanced control bit. DCB is used to minimize the short and long-term DC bias on the signal lines. This bit determines if the data is unmodified or inverted. DCA is used to validate data integrity in the embedded data stream and can also contain encoded control (VS, HS, DE). Both DCA and DCB coding schemes are generated by the serializer and decoded by the deserializer automatically. Figure 23 illustrates the serial stream per clock cycle.

NOTE

Figure 23 only illustrates the bits but does not actually represent the bit location as the bits are scrambled and balanced continuously.

DS92LV2421 DS92LV2422 30102037.gif Figure 23. Channel Link II Serial Stream (DS92LV242x)

7.3.2 Video Control Signal Filter – Serializer and Deserializer

When operating the devices in normal mode, the video control signals (DE, HS, VS) have the following restrictions:

  • Normal mode with control signal filter enabled:
    • DE and HS: Only 2 transitions per 130 clock cycles are transmitted, the transition pulse must be 3 CLK cycles or longer.
  • Normal mode with control signal filter disabled:
    • DE and HS: Only 2 transitions per 130 clock cycles are transmitted, no restriction on minimum transition pulse.
  • VS: Only 1 transition per 130 clock cycles are transmitted, minimum pulse width is 130 clock cycles.

Video control signals are defined as low frequency signals with limited transitions. Glitches of a control signal can cause a visual display error. This feature allows for the chipset to validate and filter out any high frequency noise on the control signals (see Figure 24).

DS92LV2421 DS92LV2422 video_control_signal_filter_waveform.gif Figure 24. Video Control Signal Filter Waveform

7.3.3 Serializer Functional Description

The serializer converts a wide parallel input bus to a single serial output data stream and also acts as a signal generator for the chipset Built In Self Test (BIST) mode. The device can be configured through external pins or through the optional serial control bus. The serializer features enhance signal quality on the link by supporting: a selectable VOD level, a selectable de-emphasis signal conditioning, and Channel Link II data coding that provides randomization, scrambling, and DC balancing of the data. The serializer includes multiple features to reduce EMI associated with display data transmission. This includes the randomization and scrambling of the data and system spread spectrum clock support. The serializer features power-saving features with a sleep mode, auto stop clock feature, and optional LVCMOS (1.8 V) parallel bus compatibility (see also Optional Serial Bus Control and Built-In Self Test (BIST)).

7.3.3.1 EMI Reduction Features

7.3.3.1.1 Data Randomization and Scrambling

Channel Link II serializers and deserializers feature a three-step encoding process that enables the use of AC-coupled interconnects and also helps to manage EMI. The serializer first passes the parallel data through a scrambler which randomizes the data. The randomized data is then DC-balanced. The DC-balanced and randomized data then goes through a bit-shuffling circuit and is transmitted out on the serial line. This encoding process helps to prevent static data patterns on the serial stream. The resulting frequency content of the serial stream ranges from the parallel clock frequency to the serial Nyquist rate. For example, if the serializer and deserializer chip set is operating at a parallel clock frequency of 75 MHz, the resulting frequency content of serial stream ranges from 75 MHz to 1.05 GHz (75 MHz × 28 bits / 2 = 2.1 GHz / 2 = 1.05 GHz).

7.3.3.1.2 Serializer Spread Spectrum Compatibility

The serializer CLKIN is capable of tracking spread spectrum clocking (SSC) from a host source. The CLKIN accepts spread spectrum tracking up to 35-kHz modulation and ±0.5, ±1, or ±2% deviations (center spread). The maximum conditions for the CLKIN input are: a modulation frequency of 35 kHz and amplitude deviations of ±2% (4% total).

7.3.3.2 Signal Quality Enhancers

7.3.3.2.1 Serializer VOD Select (VODSEL)

The serializer differential output voltage may be increased by setting the VODSEL pin high. When VODSEL is low, the DC VOD is at the standard (default) level. When VODSEL is high, the VOD is increased in level. The increased VOD is useful in extremely high noise environments and also on extra long cable length applications. When using de-emphasis, TI recommends setting VODSEL = H to avoid excessive signal attenuation, especially with the larger de-emphasis settings. This feature may be controlled by the external pin or by register.

Table 2. Differential Output Voltage

INPUT EFFECT
VODSEL VOD (mV) VOD (mVp-p)
H ±420 840
L ±280 560

7.3.3.2.2 Serializer De-Emphasis (De-Emph)

The de-emphasis pin controls the amount of de-emphasis beginning one full bit time after a logic transition that the serializer drives. This is useful to counteract loading effects of long or lossy cables. This pin must be left open for standard switching currents (no de-emphasis) or if controlled by register. De-emphasis is selected by connecting a resistor on this pin to ground, with R value between 0.5 kΩ to 1 MΩ, or by register setting. When using de-emphasis, TI recommends to set VODSEL = H.

Table 3. De-Emphasis Resistor Value

RESISTOR VALUE (kΩ) DE-EMPHASIS SETTING
Open Disabled
0.6 –12 dB
1 –9 dB
2 –6 dB
5 –3 dB
DS92LV2421 DS92LV2422 30110160.gif Figure 25. De-Emphasis vs R Value

7.3.3.3 Power-Saving Features

7.3.3.3.1 Serializer Power-Down Feature (PDB)

The serializer has a PDB input pin to enable or power down the device. This pin is controlled by the host and is used to save power, disabling the link when it is not needed. In power-down mode, the high-speed driver outputs are both pulled to VDD and present a 0-V VOD state.

NOTE

In power down, the optional serial bus control registers are RESET.

7.3.3.3.2 Serializer Stop Clock Feature

The serializer enters a low power SLEEP state when the CLKIN is stopped. A STOP condition is detected when the input clock frequency is less than 3 MHz. The clock must be held at a static low or high state. When the CLKIN starts again, the serializer locks to the valid input clock and then transmits the serial data to the deserializer.

NOTE

In STOP CLOCK SLEEP, the optional serial bus control register values are RETAINED.

7.3.3.3.3 1.8-V or 3.3-V VDDIO Operation

The serializer parallel bus and serial bus interface can operate with 1.8-V or 3.3-V levels (VDDIO) for host compatibility. The 1.8-V levels offer lower noise (EMI) and also system power savings.

7.3.3.3.4 Deserializer Power-Down Feature (PDB)

The deserializer has a PDB input pin to enable or power down the device. This pin can be controlled by the system to save power, disabling the deserializer when the display is not needed. An auto-detect mode is also available. In this mode, the PDB pin is tied high and the deserializer enters power down when the serial stream stops. When the serial stream starts up again, the deserializer locks to the input stream and assert the LOCK pin and output valid data. In power-down mode, the data and CLKOUT output states are determined by the OSS_SEL status.

NOTE

In power down, the optional serial bus control registers are RESET.

7.3.3.3.5 Deserializer Stop Stream SLEEP Feature

The deserializer enters a low power SLEEP state when the input serial stream is stopped. A STOP condition is detected when the embedded clock bits are not present. When the serial stream starts again, the deserializer then locks to the incoming signal and recover the data.

NOTE

In STOP STREAM SLEEP, the optional serial bus control registers values are RETAINED.

7.3.3.4 Serializer Pixel Clock Edge Select (RFB)

The RFB pin determines the edge that the data is latched on. If RFB is high, input data is latched on the rising edge of the CLKIN. If RFB is low, input data is latched on the falling edge of the CLKIN. Serializer and deserializer may be set differently. This feature may be controlled by the external pin or by register.

7.3.3.5 Optional Serial Bus Control

See Optional Serial Bus Control.

7.3.3.6 Optional BIST Mode

See Built-In Self Test (BIST).

7.3.4 Deserializer Functional Description

The deserializer converts a single input serial data stream to a wide parallel output bus and also provides a signal check for the chipset Built-In Self Test (BIST) mode. The device can be configured through external pins and strap pins or through the optional serial control bus. The deserializer features enhance signal quality on the link by supporting an equalizer input and Channel Link II data coding that provides randomization, scrambling, and DC balancing of the data. The deserializer includes multiple features to reduce EMI associated with display data transmission. This includes the randomization and scrambling of the data and output spread spectrum clock generation (SSCG) support. The deserializer features power-saving features with a power-down mode and optional LVCMOS (1.8 V) interface compatibility.

7.3.4.1 Signal Quality Enhancers

7.3.4.1.1 Deserializer Input Equalizer Gain (EQ)

The deserializer can enable receiver input equalization of the serial stream to increase the eye opening to the deserializer input.

NOTE

This function cannot be seen at the RxIN± input but can be observed at the serial test port (ROUT±) enabled through the serial bus control registers. The equalization feature may be controlled by the external pin or by register.

Table 4. Receiver Equalization Configuration Table

INPUTS EFFECT
EQ3 EQ2 EQ1 EQ0
L L L H ≈1.5 dB
L L H H ≈3 dB
L H L H ≈4.5 dB
L H H H ≈6 dB
H L L H ≈7.5 dB
H L H H ≈9 dB
H H L H ≈10.5 dB
H H H H ≈12 dB
X X X L OFF(1)
(1) Default Setting is EQ = Off

7.3.4.2 EMI Reduction Features

7.3.4.2.1 Deserializer Output Slew Rate Select (OS_CLKOUT/OS_DATA)

The parallel bus outputs (DO[23:0], CO[3:1], and CLKOUT) of the deserializer feature a selectable output slew. The DATA (DO[23:0], CO[3:1]) are controlled by strap pin or register bit OS_DATA. The CLKOUT is controlled by strap pin or register bit OS_CLKOUT. When the OS_CLKOUT/DATA = H, the maximum slew rate is selected. When the OS_PCLK/DATA = L, the minimum slew rate is selected. Use the higher slew rate setting when driving longer traces or a heavier capacitive load.

7.3.4.2.2 Deserializer Common-Mode Filter Pin (CMF) (Optional)

The deserializer provides access to the center tap of the internal termination. A capacitor may be placed on this pin for additional common-mode filtering of the differential pair. This can be useful in high-noise environments for additional noise rejection capability. A 4.7-µF capacitor may be connected from this pin to Ground.

7.3.4.2.3 Deserializer SSCG Generation (Optional)

The deserializer provides an internally generated spread spectrum clock (SSCG) to modulate its outputs. Both clock and data outputs are modulated. This aids to lower system EMI. Output SSCG deviations of ±2% (4% total) at up to 100-kHz modulations are available (see Table 5). This feature may be controlled by external strap pins or by register.

NOTE

The device supports SSCG function with CLKOUT = 10 MHz to 65 MHz. When the CLKOUT = 65 MHz to 75 MHz, it is required to disable the SSCG function (SSC[3:0] = 0000).

DS92LV2421 DS92LV2422 30110133.gif Figure 26. SSCG Waveform

Table 5. SSCG Configuration (LF_MODE = L) – Deserializer Output

SSC[3:0] INPUTS
LF_MODE = L (20 - 65 MHz)
RESULT
SSC3 SSC2 SSC1 SSC0 fdev (%) fmod (kHz)
L L L L Off Off
L L L H ±0.5 CLK/2168
L L H L ±1
L L H H ±1.5
L H L L ±2
L H L H ±0.5 CLK/1300
L H H L ±1
L H H H ±1.5
H L L L ±2
H L L H ±0.5 CLK/868
H L H L ±1
H L H H ±1.5
H H L L ±2
H H L H ±0.5 CLK/650
H H H L ±1
H H H H ±1.5

Table 6. SSCG Configuration (LF_MODE = H) – Deserializer Output

SSC[3:0] INPUTS
LF_MODE = H (10 - 20 MHz)
RESULT
SSC3 SSC2 SSC1 SSC0 fdev (%) fmod (kHz)
L L L L Off Off
L L L H ±0.5 CLK/620
L L H L ±1
L L H H ±1.5
L H L L ±2
L H L H ±0.5 CLK/370
L H H L ±1
L H H H ±1.5
H L L L ±2
H L L H ±0.5 CLK/258
H L H L ±1
H L H H ±1.5
H H L L ±2
H H L H ±0.5 CLK/192
H H H L ±1
H H H H ±1.5

7.3.4.2.4 1.8-V or 3.3-V VDDIO Operation

The deserializer parallel bus and serial bus interface can operate with 1.8-V or 3.3-V levels (VDDIO) for target (display) compatibility. The 1.8-V levels offer a lower noise (EMI) and also system power savings.

7.3.4.3 Deserializer Clock-Data Recovery Status Flag (LOCK) And Output State Select (OSS_SEL)

When PDB is driven high, the CDR PLL begins locking to the serial input and LOCK goes from TRI-STATE to low (depending on the value of the OSS_SEL setting). After the DS92LV2422 completes its lock sequence to the input serial data, the LOCK output is driven high, indicating valid data and clock recovered from the serial input is available on the parallel bus and clock outputs. The CLKOUT output is held at its current state at the change from OSC_CLK (if this is enabled through OSC_SEL) to the recovered clock (or vice versa).

If there is a loss of clock from the input serial stream, LOCK is driven low and the state of the outputs are based on the OSS_SEL setting (strap pin configuration or register).

7.3.4.4 Deserializer Oscillator Output (Optional)

The deserializer provides an optional clock output when the input clock (serial stream) has been lost. This is based on an internal oscillator. The frequency of the oscillator may be selected. This feature may be controlled by the external pin or by register (see Table 8 and Table 9).

Table 7. OSS_SEL and PDB Configuration (Deserializer Outputs)

INPUTS OUTPUTS
SERIAL INPUT PDB OSS_SEL CLKOUT DO[23:0], CO1, CO2, CO3 LOCK PASS
X L L Z Z Z Z
X L H Z Z Z Z
Static H L L L L L
Static H H Z Z(1) L L
Active H X Active Active H H
(1) If DO[23:0], CO[3:1] pin is strapped high, the output is pulled up.

Table 8. OSC (Oscillator) Mode — Deserializer Output

INPUTS OUTPUTS
EMBEDDED CLK CLKOUT DO[23:0], CO1, CO2, CO3 LOCK PASS
See (1) OSC Output L L H
Present Toggling Active H H
(1) Absent and OSC_SEL ≠ 000.
DS92LV2421 DS92LV2422 30065340.gif Figure 27. Deserializer Outputs With Output State Select Low (OSS_SEL = L)
DS92LV2421 DS92LV2422 30065353.gif Figure 28. Deserializer Outputs With Output State Select High (OSS_SEL = H)

Table 9. OSC_SEL (Oscillator) Configuration

OSC_SEL[2:0] INPUTS CLKOUT OSCILLATOR FREQUENCY
OSC_SEL2 OSC_SEL1 OSC_SEL0
L L L Off – Feature Disabled – Default
L L H 50 MHz ± 40%
L H L 25 MHz ± 40%
L H H 16.7 MHz ± 40%
H L L 12.5 MHz ± 40%
H L H 10 MHz ± 40%
H H L 8.3 MHz ± 40%
H H H 6.3 MHz ± 40%
DS92LV2421 DS92LV2422 30065354.gif Figure 29. Deserializer Outputs With Output State High and CLKOUT Oscillator Option Enabled

7.3.4.5 Deserializer OP_LOW (Optional)

The OP_LOW feature is used to hold the LVCMOS outputs (except for the LOCK output) at a low state. The user must toggle the OP_LOW set / reset register bit to release the outputs to the normal toggling state.

NOTE

The release of the outputs can only occur when LOCK is high. When the OP_LOW feature is enabled, anytime LOCK = low, the LVCMOS outputs toggle to a low state again. The OP_LOW strap pin feature is assigned to output PASS pin 42.

Restrictions on other straps:

  1. Other straps must not be used to keep the data and clock outputs at a true low state. Other features must be selected through I2C.
  2. The OSS_SEL function is not available when OP_LOW is enabled (tied high).

Outputs DO[23:0], CO[3:1], and CLKOUT are in TRI-STATE before PDB toggles high, because the OP_LOW strap value has not been recognized until the DS92LV2422 powers up. Figure 30 shows the user controlled release of OP_LOW and automatic reset of OP_LOW set on the falling edge of LOCK. Figure 31 shows the user controlled release of OP_LOW and manual reset of OP_LOW set.

NOTE

Manual reset of OP_LOW can only occur when LOCK is high.

DS92LV2421 DS92LV2422 30110165.gif Figure 30. OP_LOW Auto Set
DS92LV2421 DS92LV2422 30110166.gif Figure 31. OP_LOW Manual Set or Reset

7.3.4.6 Deserializer Clock Edge Select (RFB)

The RFB pin determines the edge that the data is strobed on. If RFB is high, output data is strobed on the rising edge of CLKOUT. If RFB is low, data is strobed on the falling edge of CLKOUT. This allows for inter-operability with downstream devices. The deserializer output does not need to use the same edge as the serializer input. This feature may be controlled by the external pin or by register.

7.3.4.7 Deserializer Control Signal Filter (Optional)

The deserializer provides an optional control signal (C3, C2, C1) filter that monitors the three control signals and eliminates any pulses or glitches that are 1 or 2 CLKOUT periods wide. Control signals must be 3 parallel clock periods wide (in its high or low state, regardless of which state is active). This is set by the CONFIG[1:0] strap option or by I2C register control.

7.3.4.8 Deserializer Low Frequency Optimization (LF_Mode)

This feature may be controlled by the external pin or by register.

7.3.4.9 Deserializer Map Select

This feature may be controlled by the external pin or by register.

Table 10. Map Select Configuration

INPUTS EFFECT
MAP_SEL1 MAP_SEL0
L L Bit 4, Bit 5 on LSB
DEFAULT
L H LSB 0 or 1
H H or L LSB 0

7.3.4.10 Deserializer Strap Input Pins

Configuration of the device may be done through configuration input pins and the strap input pins, or through the serial control bus. The strap input pins share select parallel bus output pins. They are used to load in configuration values during the initial power-up sequence of the device. Only a pullup on the pin is required when a high is desired. By default, the pad has an internal pulldown and bias low by itself. The recommended value of the pullup is 10 kΩ to VDDIO; open (NC) for low, because no pulldown is required (internal pulldown). If using the serial control bus, no pullups are required.

7.3.4.11 Optional Serial Bus Control

See Optional Serial Bus Control.

7.3.4.12 Optional BIST Mode

See Built-In Self Test (BIST).

7.3.5 Built-In Self Test (BIST)

An optional At-Speed Built-In Self Test (BIST) feature supports the testing of the high-speed serial link. This is useful in the prototype stage, equipment production, in-system test, and for system diagnostics. In BIST mode, only an input clock is required along with control to the serializer and deserializer BISTEN input pins. The serializer outputs a test pattern (PRBS-7) and drives the link at speed. The deserializer detects the PRBS-7 pattern and monitors it for errors. A PASS output pin toggles to flag any payloads that are received with 1 to 24 errors. Upon completion of the test, the result of the test is held on the PASS output until reset (new BIST test or power down). A high on PASS indicates NO ERRORS were detected. A low on PASS indicates one or more errors were detected. The duration of the test is controlled by the pulse width applied to the deserializer BISTEN pin. During the BIST duration, the deserializer data outputs toggle with a checkerboard pattern.

Inter-operability is supported between this Channel Link II device and all Channel Link II generations (Gen 1, 2, 3). See Sample BIST Sequence for entering BIST mode and control.

7.3.5.1 Sample BIST Sequence

See Figure 32 for the BIST mode flow diagram.

Step 1: Place the DS92LV2421 serializer in BIST Mode by setting serializer BISTEN = H. For the DS92LV2421 serializer or DS99R421-Q1 FPD-Link II serializer, BIST Mode is enabled through the BISTEN pin. For the DS90C241 serializer or DS90UR241 serializer, BIST mode is entered by setting all the input data of the device to a low state. A CLKIN is required for BIST. When the deserializer detects the BIST mode pattern and command (DCA and DCB code), the data and control signal outputs are shut off.

Step 2: Place the DS92LV2422 deserializer in BIST mode by setting BISTEN = H. The deserializer is now in BIST mode and checks the incoming serial payloads for errors. If an error in the payload (1 to 24) is detected, the PASS pin switches low for one half of the clock period. During the BIST test, the PASS output can be monitored and counted to determine the payload error rate.

Step 3: To stop BIST mode, the deserializer BISTEN pin is set low. The deserializer stops checking the data, and the final test result is held on the PASS pin. If the test ran error free, the PASS output is high. If there was one or more errors detected, the PASS output is low. The PASS output state is held until a new BIST is run, the device is RESET, or powered down. The BIST duration is user controlled by the duration of the BISTEN signal.

Step 4: To return the link to normal operation, the serializer BISTEN input is set low. The Link returns to normal operation.

Figure 33 shows the waveform diagram of a typical BIST test for two cases. Case 1 is error-free, and Case 2 shows one with multiple errors. In most cases, it is difficult to generate errors due to the robustness of the link (differential data transmission and so forth), thus they may be introduced by greatly extending the cable length, faulting the interconnect, or reducing signal condition enhancements (de-emphasis, VODSEL, or Rx equalization).

DS92LV2421 DS92LV2422 30110143.gif Figure 32. BIST Mode Flow Diagram
DS92LV2421 DS92LV2422 30110164.gif Figure 33. BIST Waveforms

7.3.5.2 BER Calculations

It is possible to calculate the approximate Bit Error Rate (BER). The following is required:

  • Clock Frequency (MHz)
  • BIST Duration (seconds)
  • BIST Test Result (PASS)

The BER is less than or equal to one over the product of 24 times the CLKOUT rate times the test duration. If we assume a 65-MHz clock, a 10-minute (600 seconds) test, and a PASS, the BER is ≤ 1.07 X 10E-12.

BIST mode runs a check on the data payload bits. The LOCK pin also provides a link status. If the recovery of the C0 and C1 bits does not reconstruct the expected clock signal, the LOCK pin switches low. The combination of the LOCK and At-Speed BIST PASS pin provides a powerful tool for system evaluation and performance monitoring.

7.3.6 Optional Serial Bus Control

The serializer and deserializer may also be configured by the use of a serial control bus that is I2C protocol-compatible. By default, the I2C Reg 0x00 = 0x00, and all configuration is set by control or strap pins. Writing reg 0x00 = 0x01 enables or allows configuration by registers; this overrides the control or strap pins. Multiple devices may share the serial control bus, because multiple addresses are supported (see Figure 34).

The serial bus is comprised of three pins. The SCL is a serial bus clock input. The SDA is the serial bus data input or output signal. Both SCL and SDA signals require an external pullup resistor to VDDIO. For most applications, a 4.7-kΩ pullup resistor to VDDIO may be used. The resistor value may be adjusted for capacitive loading and data rate requirements. The signals are either pulled high or driven low.

DS92LV2421 DS92LV2422 30110141.gif Figure 34. Serial Control Bus Connection

The third pin is the ID[X] pin. This pin sets one of four possible device addresses. Two different connections are possible:

  • The pin may be pulled to VDD (1.8 V, not VDDIO) with a 10-kΩ resistor.
  • The pin may be pulled to VDD (1.8 V, not VDDIO) with a 10-kΩ resistor and pulled down to ground with a recommended value RID resistor. This creates a voltage divider that sets the other three possible addresses.

See Table 11 for the serializer and Table 12 for the deserializer. Do not tie ID[X] directly to VSS.

Table 11. ID[X] Resistor Value – DS92LV2421 (Serializer)

RESISTOR
RID kΩ(1)
(5% TOL)
ADDRESS
7'b
ADDRESS
8'b
0 APPENDED (WRITE)
0.47 7b' 110 1001 (h'69) 8b' 1101 0010 (h'D2)
2.7 7b' 110 1010 (h'6A) 8b' 1101 0100 (h'D4)
8.2 7b' 110 1011 (h'6B) 8b' 1101 0110 (h'D6)
Open 7b' 110 1110 (h'6E) 8b' 1101 1100 (h'DC)
(1) RID ≠ 0 Ω. Do not connect directly to VSS (GND). This is not a valid address.

Table 12. ID[X] Resistor Value – DS92LV2422 Deserializer

RESISTOR
RID kΩ(1)
(5% TOL)
ADDRESS
7'b
ADDRESS
8'b
0 APPENDED (WRITE)
0.47 7b' 111 0001 (h'71) 8b' 1110 0010 (h'E2)
2.7 7b' 111 0010 (h'72) 8b' 1110 0100 (h'E4)
8.2 7b' 111 0011 (h'73) 8b' 1110 0110 (h'E6)
Open 7b' 111 0110 (h'76) 8b' 1110 1100 (h'EC)
(1) RID ≠ 0 Ω. Do not connect directly to VSS (GND). This is not a valid address.

The serial bus protocol is controlled by START, START-repeated, and STOP phases. A START occurs when SCL transitions low while SDA is high. A STOP occurs when SDA transition high while SCL is also high (see Figure 35).

DS92LV2421 DS92LV2422 30110151.gif Figure 35. START and STOP Conditions

To communicate with a remote device, the host controller (master) sends the slave address and listens for a response from the slave. This response is referred to as an acknowledge bit (ACK). If a slave on the bus is addressed correctly, it Acknowledges (ACKs) the master by driving the SDA bus low. If the address doesn't match the slave address of a device, it Not-acknowledges (NACKs) the master by letting SDA be pulled high. ACKs also occur on the bus when data is being transmitted. When the master is writing data, the slave ACKs after every data byte is successfully received. When the master is reading data, the master ACKs after every data byte is received to let the slave know it wants to receive another data byte. When the master wants to stop reading, it NACKs after the last data byte and creates a stop condition on the bus. All communication on the bus begins with either a start condition or a repeated start condition. All communication on the bus ends with a stop condition. A READ is shown in Figure 36 and a WRITE is shown in Figure 37.

NOTE

During initial power-up, a delay of 10 ms is required before the I2C will respond.

If the serial bus is not required, the three pins may be left open (NC).

DS92LV2421 DS92LV2422 30110138.gif Figure 36. Serial Control Bus — READ
DS92LV2421 DS92LV2422 30110139.gif Figure 37. Serial Control Bus — WRITE

7.4 Device Functional Modes

7.4.1 Serializer and Deserializer Operating Modes and Reverse Compatibility (CONFIG[1:0])

The DS92LV242x chipset is compatible with other single serial lane Channel Link II or FPD-Link II devices. Configuration modes are provided for reverse compatibility with the DS90C241 / DS90C124 chipset (FPD-Link II Generation 1) and also the DS90UR241 / DS90UR124 chipset (FPD-Link II Generation 2) by setting the respective mode with the CONFIG[1:0] pins on the serializer or deserializer as shown in Table 13 and Table 14. This selection also determines whether the control signal filter feature is enabled or disabled in the normal mode. This feature may be controlled by pin or by register.

Table 13. DS92LV2421 Serializer Modes

CONFIG1 CONFIG0 MODE COMPATIBLE DESERIALIZER DEVICE
L L Normal Mode, Control Signal Filter disabled DS92LV2422, DS92LV2412,
DS92LV0422, DS92LV0412
L H Normal Mode, Control Signal Filter enabled DS92LV2422, DS92LV2412,
DS92LV0422, DS92LV0412
H L Reverse Compatibility Mode (FPD-Link II, GEN2) DS90UR124, DS99R124Q-Q1
H H Reverse Compatibility Mode (FPD-Link II, GEN1) DS90C124

Table 14. DS92LV2422 Deserializer Modes

CONFIG1 CONFIG0 MODE COMPATIBLE SERIALIZER DEVICE
L L Normal Mode, Control Signal Filter disabled DS92LV2421, DS92LV2411, DS92LV0421, DS92LV0411
L H Normal Mode, Control Signal Filter enabled DS92LV2421, DS92LV2411, DS92LV0421, DS92LV0411
H L Reverse Compatibility Mode (FPD-Link II, GEN2) DS90UR241, DS99R421-Q1
H H Reverse Compatibility Mode (FPD-Link II, GEN1) DS90C241

7.5 Register Maps

Table 15. SERIALIZER — Serial Bus Control Registers

ADD
(DEC)
ADD
(HEX)
REGISTER NAME BIT(S) R/W DEFAULT
(BIN)
FUNCTION DESCRIPTION
0 0 Serializer Config 1 7 R/W 0 Reserved Reserved
6 R/W 0 Reserved Reserved
5 R/W 0 VODSEL 0: Low
1: High
4 R/W 0 RFB 0: Data latched on Falling edge of CLKIN
1: Data latched on Rising edge of CLKIN
3:2 R/W 00 CONFIG 00: Normal Mode, Control Signal Filter Disabled
01: Normal Mode, Control Signal Filter Enabled
10: DS90UR124, DS99R124Q-Q1 Reverse-Compatibility Mode (FPD-Link II, GEN2)
11: DS90C124 Reverse-Compatibility Mode (FPD-Link II, GEN1)
1 R/W 0 SLEEP Note – not the same function as PowerDown (PDB)
0: Normal Mode
1: Sleep Mode – Register settings retained.
0 R/W 0 REG 0: Configurations set from control pins
1: Configuration set from registers (except I2C_ID)
1 1 Device ID 7 R/W 0 REG ID 0: Address from ID[X] Pin
1: Address from Register
6:0 R/W 1101000 ID[X] Serial Bus Device ID, Four IDs are:
7b '1101 001 (h'69)
7b '1101 010 (h'6A)
7b '1101 011 (h'6B)
7b '1101 110 (h'6E)
All other addresses are reserved.
2 2 De-Emphasis Control 7:5 R/W 000 De-Emphasis Setting 000: set by external resistor
001: –1 dB
010: –2 dB
011: –3.3 dB
100: –5 dB
101: –6.7 dB
110: –9 dB
111: –12 dB
4 R/W 0 De-Emphasis EN 0: De-emphasis enabled
1: De-emphasis disabled
3:0 R/W 000 Reserved Reserved

Table 16. DESERIALIZER — Serial Bus Control Registers

ADD
(DEC)
ADD
(HEX)
REGISTER NAME BIT(S) R/W DEFAULT
(BIN)
FUNCTION DESCRIPTION
0 0 Deserializer Config 1 7 R/W 0 LF_MODE 0: 20 to 65 MHz SSCG Operation
1: 10 to 20 MHz SSCG Operation
6 R/W 0 OS_CLKOUT 0: Normal CLKOUT Slew Rate
1: Increased CLKOUT Slew Rate
5 R/W 0 OS_DATA 0: Normal DATA Slew Rate
1: Increased DATA Slew Rate
4 R/W 0 RFB 0: Data strobed on Falling edge of CLKOUT
1: Data strobed on Rising edge of CLKOUT
3:2 R/W 00 CONFIG 00: Normal Mode, Control Signal Filter Disabled
01: Normal Mode, Control Signal Filter Enabled
10: DS90UR241, DS99R241-Q1 Reverse-Compatibility Mode (FPD-Link II, GEN2)
11: DS90C241 Reverse-Compatibility Mode (FPD-Link II, GEN1)
1 R/W 0 SLEEP Note – not the same function as PowerDown (PDB)
0: Normal Mode
1: Sleep Mode – Register settings retained.
0 R/W 0 REG Control 0: Configurations set from control pins or strap pins
1: Configurations set from registers (except I2C_ID)
1 1 Slave ID 7 R/W 0 REG ID 0: Address from ID[X] Pin
1: Address from Register
6:0 R/W 1110000 ID[X] Serial Bus Device ID, Four IDs are:
7b '1110 001 (h'71)
7b '1110 010 (h'72)
7b '1110 011 (h'73)
7b '1110 110 (h'76)
All other addresses are Reserved.
2 2 Deserializer Features 1 7 R/W 0 OP_LOW 0: Set outputs state LOW (except LOCK)
1: Release output LOW state, outputs toggling normally
Note: This register only works during LOCK = 1
6 R/W 0 OSS_SEL Output Sleep State Select
0: CLKOUT, DO[23:0], CO1, CO2, CO3 = L, LOCK = Normal, PASS = H
1: CLKOUT, DO[23:0], CO1, CO2, CO3 = Tri-State, LOCK = Normal, PASS = H
5:4 R/W 00 MAP_SEL Special for Reverse-Compatibility Mode
00: Bit 4, 5 on LSB
01: LSB zero if all data is zero; one if any data is one
10: LSB zero
11: LSB zero
3 R/W 0 OP_LOW Strap Bypass 0: Strap will determine whether OP_LOW feature is ON or OFF
1: Turns OFF OP_LOW feature
2:0 R/W 00 OSC_SEL 000: Disable
001: 50 MHz ± 40%
010: 25 MHz ± 40%
011: 16.7 MHz ± 40%
100: 12.5 MHz ± 40%
101: 10 MHz ± 40%
110: 8.3 MHz ± 40%
111: 6.3 MHz ± 40%
3 3 Deserializer Features 2 7:5 R/W 000 EQ Gain 000: ≈1.625 dB
001: ≈3.25 dB
010: ≈4.87 dB
011: ≈6.5 dB
100: ≈8.125 dB
101: ≈9.75 dB
110: ≈11.375 dB
111: ≈13 dB
4 R/W 0 EQ Enable 0: EQ = disable
1: EQ = enable
3:0 R/W 0000 SSC If LF_MODE = 0, then:
000: SSCG disable
0001: fdev = ±0.5%, fmod = CLK/2168
0010: fdev = ±1.0%, fmod = CLK/2168
0011: fdev = ±1.5%, fmod = CLK/2168
0100: fdev = ±2.0%, fmod = CLK/2168
0101: fdev = ±0.5%, fmod = CLK/1300
0110: fdev = ±1.0%, fmod = CLK/1300
0111: fdev = ±1.5%, fmod = CLK/1300
1000: fdev = ±2.0%, fmod = CLK/1300
1001: fdev = ±0.5%, fmod = CLK/868
1010: fdev = ±1.0%, fmod = CLK/868
1011: fdev = ±1.5%, fmod = CLK/868
1100: fdev = ±2.0%, fmod = CLK/868
1101: fdev = ±0.5%, fmod = CLK/650
1110: fdev = ±1.0%, fmod = CLK/650
1111: fdev = ±1.5%, fmod = CLK/650
If LF_MODE = 1, then:
000: SSCG disable
0001: fdev = ±0.5%, fmod = CLK/620
0010: fdev = ±1.0%, fmod = CLK/620
0011: fdev = ±1.5%, fmod = CLK/620
0100: fdev = ±2.0%, fmod = CLK/620
0101: fdev = ±0.5%, fmod = CLK/370
0110: fdev = ±1.0%, fmod = CLK/370
0111: fdev = ±1.5%, fmod = CLK/370
1000: fdev = ±2.0%, fmod = CLK/370
1001: fdev = ±0.5%, fmod = CLK/258
1010: fdev = ±1.0%, fmod = CLK/258
1011: fdev = ±1.5%, fmod = CLK/258
1100: fdev = ±2.0%, fmod = CLK/258
1101: fdev = ±0.5%, fmod = CLK/192
1110: fdev = ±1.0%, fmod = CLK/192
1111: fdev = ±1.5%, fmod = CLK/192
4 4 ROUT Config 7 R/W 0 Repeater Enable 0: Output ROUT± = disable
1: Output ROUT± = enable
6:0 R/W 0000000 Reserved Reserved