ZHCSIJ2B
july 2018 – march 2023
DS90UB935-Q1
PRODUCTION DATA
1
1
特性
2
应用
3
说明
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
建议运行条件
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
推荐的串行控制总线时序
6.7
Timing Diagrams
6.8
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
CSI-2 Receiver
7.3.1.1
CSI-2 Receiver Operating Modes
7.3.1.2
CSI-2 Receiver High-Speed Mode
7.3.1.3
CSI-2 Protocol Layer
7.3.1.4
CSI-2 Short Packet
7.3.1.5
CSI-2 Long Packet
7.3.1.6
CSI-2 Errors and Detection
7.3.1.6.1
CSI-2 ECC Detection and Correction
7.3.1.6.2
CSI-2 Check Sum Detection
7.3.1.6.3
CSI-2 Receiver Status
7.3.2
FPD-Link III Forward Channel Transmitter
7.3.2.1
Frame Format
7.3.3
FPD-Link III Back Channel Receiver
7.3.4
Serializer Status and Monitoring
7.3.4.1
Forward Channel Diagnostics
7.3.4.2
Back Channel Diagnostics
7.3.4.3
Voltage and Temperature Sensing
7.3.4.3.1
Programming Example
7.3.4.4
Built-In Self Test
7.3.5
FrameSync Operation
7.3.5.1
External FrameSync
7.3.5.2
Internally Generated FrameSync
7.3.6
GPIO Support
7.3.6.1
GPIO Status
7.3.6.2
GPIO Input Control
7.3.6.3
GPIO Output Control
7.3.6.4
Forward Channel GPIO
7.3.6.5
Back Channel GPIO
7.4
Device Functional Modes
7.4.1
Clocking Modes
7.4.1.1
Synchronous Mode
7.4.1.2
Non-Synchronous Clock Mode
7.4.1.3
Non-Synchronous Internal Mode
7.4.1.4
DVP Backwards Compatibility Mode
7.4.1.5
Configuring CLK_OUT
7.4.2
MODE
7.5
Programming
7.5.1
I2C Interface Configuration
7.5.1.1
CLK_OUT/IDX
7.5.1.1.1
IDX
7.5.2
I2C Interface Operation
7.5.3
I2C Timing
7.6
Pattern Generation
7.6.1
Reference Color Bar Pattern
7.6.2
Fixed Color Patterns
7.6.3
Packet Generator Programming
7.6.3.1
Determining Color Bar Size
7.6.4
Code Example for Pattern Generator
7.7
Register Maps
7.7.1
I2C Device ID Register
7.7.2
Reset
7.7.3
General Configuration
7.7.4
Forward Channel Mode Selection
7.7.5
BC_MODE_SELECT
7.7.6
PLL Clock Control
7.7.7
Clock Output Control 0
7.7.8
Clock Output Control 1
7.7.9
Back Channel Watchdog Control
7.7.10
I2C Control 1
7.7.11
I2C Control 2
7.7.12
SCL High Time
7.7.13
SCL Low Time
7.7.14
Local GPIO DATA
7.7.15
GPIO Input Control
7.7.16
DVP_CFG
7.7.17
DVP_DT
7.7.18
Force BIST Error
7.7.19
Remote BIST Control
7.7.20
Sensor Voltage Gain
7.7.21
Sensor Control 0
7.7.22
Sensor Control 1
7.7.23
Voltage Sensor 0 Thresholds
7.7.24
Voltage Sensor 1 Thresholds
7.7.25
Temperature Sensor Thresholds
7.7.26
CSI-2 Alarm Enable
7.7.27
Alarm Sense Enable
7.7.28
Back Channel Alarm Enable
7.7.29
CSI-2 Polarity Select
7.7.30
CSI-2 LP Mode Polarity
7.7.31
CSI-2 High-Speed RX Enable
7.7.32
CSI-2 Low Power Enable
7.7.33
CSI-2 Termination Enable
7.7.34
CSI-2 Packet Header Control
7.7.35
Back Channel Configuration
7.7.36
Datapath Control 1
7.7.37
Remote Partner Capabilities 1
7.7.38
Partner Deserializer ID
7.7.39
Target 0 ID
7.7.40
Target 1 ID
7.7.41
Target 2 ID
7.7.42
Target 3 ID
7.7.43
Target 4 ID
7.7.44
Target 5 ID
7.7.45
Target 6 ID
7.7.46
Target 7 ID
7.7.47
Target 0 Alias
7.7.48
Target 1 Alias
7.7.49
Target 2 Alias
7.7.50
Target 3 Alias
7.7.51
Target 4 Alias
7.7.52
Target 5 Alias
7.7.53
Target 6 Alias
7.7.54
Target 7 Alias
7.7.55
Back Channel Control
7.7.56
Revision ID
7.7.57
Device Status
7.7.58
General Status
7.7.59
GPIO Pin Status
7.7.60
BIST Error Count
7.7.61
CRC Error Count 1
7.7.62
CRC Error Count 2
7.7.63
Sensor Status
7.7.64
Sensor V0
7.7.65
Sensor V1
7.7.66
Sensor T
7.7.67
CSI-2 Error Count
7.7.68
CSI-2 Error Status
7.7.69
CSI-2 Errors Data Lanes 0 and 1
7.7.70
CSI-2 Errors Data Lanes 2 and 3
7.7.71
CSI-2 Errors Clock Lane
7.7.72
CSI-2 Packet Header Data
7.7.73
Packet Header Word Count 0
7.7.74
Packet Header Word Count 1
7.7.75
CSI-2 ECC
7.7.76
IND_ACC_CTL
7.7.77
IND_ACC_ADDR
7.7.78
IND_ACC_DATA
7.7.79
FPD3_TX_ID0
7.7.80
FPD3_TX_ID1
7.7.81
FPD3_TX_ID2
7.7.82
FPD3_TX_ID3
7.7.83
FPD3_TX_ID4
7.7.84
FPD3_TX_ID5
7.7.85
Indirect Access Registers
7.7.85.1
PGEN_CTL
7.7.85.2
PGEN_CFG
7.7.85.3
PGEN_CSI_DI
7.7.85.4
PGEN_LINE_SIZE1
7.7.85.5
PGEN_LINE_SIZE0
7.7.85.6
PGEN_BAR_SIZE1
7.7.85.7
PGEN_BAR_SIZE0
7.7.85.8
PGEN_ACT_LPF1
7.7.85.9
PGEN_ACT_LPF0
7.7.85.10
PGEN_TOT_LPF1
7.7.85.11
PGEN_TOT_LPF0
7.7.85.12
PGEN_LINE_PD1
7.7.85.13
PGEN_LINE_PD0
7.7.85.14
PGEN_VBP
7.7.85.15
PGEN_VFP
7.7.85.16
PGEN_COLOR0
7.7.85.17
PGEN_COLOR1
7.7.85.18
PGEN_COLOR2
7.7.85.19
PGEN_COLOR3
7.7.85.20
PGEN_COLOR4
7.7.85.21
PGEN_COLOR5
7.7.85.22
PGEN_COLOR6
7.7.85.23
PGEN_COLOR7
7.7.85.24
PGEN_COLOR8
7.7.85.25
PGEN_COLOR9
7.7.85.26
PGEN_COLOR10
7.7.85.27
PGEN_COLOR11
7.7.85.28
PGEN_COLOR12
7.7.85.29
PGEN_COLOR13
7.7.85.30
PGEN_COLOR14
7.7.85.31
PGEN_COLOR15
8
Application and Implementation
8.1
Application Information
8.1.1
Power-over-Coax
8.2
Typical Applications
8.2.1
Design Requirements
8.2.2
Detailed Design Procedure
8.2.2.1
CSI-2 Interface
8.2.2.2
FPD-Link III Input / Output
8.2.2.3
Internal Regulator Bypassing
8.2.2.4
Loop Filter Decoupling
8.2.3
Application Curve
9
Power Supply Recommendations
9.1
Power-Up Sequencing
9.1.1
System Initialization
9.2
Power Down (PDB)
10
Layout
10.1
Layout Guidelines
10.1.1
CSI-2 Guidelines
10.2
Layout Examples
11
Device and Documentation Support
11.1
Documentation Support
11.1.1
Related Documentation
11.2
Receiving Notification of Documentation Updates
11.3
支持资源
11.4
Trademarks
11.5
静电放电警告
11.6
术语表
12
Mechanical, Packaging, and Orderable Information
封装选项
机械数据 (封装 | 引脚)
RHB|32
MPQF130D
散热焊盘机械数据 (封装 | 引脚)
RHB|32
QFND643
订购信息
zhcsij2b_oa
zhcsij2b_pm
1
特性
符合面向汽车应用的 AEC-Q100标准:
器件温度:环境工作温度范围为 -40°C 至
+105°C
符合 ISO 10605 和 IEC 61000-4-2 ESD 标准
同轴电缆供电 (PoC) 兼容收发器
符合 D-PHY v1.2 和 CSI-2 v1.3 标准的系统接口
高达 2.528Gbps 的 CSI-2 带宽
支持多达四个虚拟通道
精密多摄像头时钟和同步
灵活的可编程输出时钟发生器
高级数据保护和诊断,包括
CRC 数据保护、
传感器数据完整性检查
、I2C 写保护
、
电压和温度测量
、可编程警报
以及线路故障检测
支持单端同轴或屏蔽双绞线 (STP) 电缆
超低延迟双向 I2C 和 GPIO 控制通道支持从 ECU 侧进行 ISP 控制
1.8V 单电源
低功耗(
0.28
W 典型值)
兼容 DS90UB936-Q1、DS90UB954-Q1、DS90UB960-Q1、DS90UB934-Q1、DS90UB914A-Q1 解串器
宽温度范围:–40°C 至 105°C
小型 5mm × 5mm VQFN 封装和 PoC 解决方案尺寸,适合紧凑型摄像头模块设计