ZHCSO34F April   2011  – August 2021 DS80PCI402

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings (1) (1) (1)
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Ratings
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Electrical Characteristics — Serial Management Bus Interface
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 15
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 4-Level Input Configuration Guidelines
    4. 8.4 Device Functional Modes
      1. 8.4.1 Pin Control Mode
      2. 8.4.2 SMBUS Mode
    5. 8.5 Programming
      1. 8.5.1 System Management Bus (SMBus) and Configuration Registers
      2. 8.5.2 Transfer of Data Through the SMBus
      3. 8.5.3 Writing a Register
      4. 8.5.4 Reading a Register
      5. 8.5.5 SMBus Controller Mode
    6. 8.6 Register Maps
      1.      31
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 3.3-V or 2.5-V Supply Mode Operation
    2. 10.2 Power Supply Bypassing
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 PCB Layout Considerations for Differential Pairs
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 接收文档更新通知
    2. 12.2 支持资源
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 术语表
  13. 13Mechanical, Packaging, and Orderable Information

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6.6 Electrical Characteristics — Serial Management Bus Interface

Over recommended operating supply and temperature ranges unless other specified.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SERIAL BUS INTERFACE DC SPECIFICATIONS
VIL Data, clock input low voltage 0.8 V
VIH Data, clock input high voltage 2.1 3.6 V
IPULLUP Current through pullup resistor or current source High Power Specification 4 mA
VDD Nominal bus voltage 2.375 3.6 V
ILEAK-Bus Input leakage per bus segment (1) -200 +200 µA
ILEAK-Pin Input leakage per device pin -15 µA
CI Capacitance for SDA and SCL (1) (2) 10 pF
RTERM External termination resistance pull to VDD = 2.5 V ± 5% OR 3.3 V ± 10% Pullup VDD = 3.3 V,
(1)(2)(3)		 2000 Ω
Pullup VDD = 2.5 V,
(1)(2)(3)		 1000 Ω
SERIAL BUS INTERFACE TIMING SPECIFICATIONS
FSMB Bus operating frequency ENSMB = VDD (Reader mode) 400 kHz
ENSMB = FLOAT (Controller mode) 280 400 520 kHz
TBUF Bus free time between stop and start condition 1.3 µs
THD:STA Hold time after (repeated) start condition. After this period, the first clock is generated. At IPULLUP, Max 0.6 µs
TSU:STA Repeated start condition setup time 0.6 µs
TSU:STO Stop condition setup time 0.6 µs
THD:DAT Data hold time 0 ns
TSU:DAT Data setup time 100 ns
TLOW Clock low period 1.3 µs
THIGH Clock high period  (4) 0.6 50 µs
tF Clock/data fall time  (4) 300 ns
tR Clock/data rise time  (4) 300 ns
tPOR Time in which a device must be operational after power-on reset (4) (5) 500 ms
(1) Recommended value.
(2) Recommended maximum capacitance load per bus segment is 400 pF.
(3) Maximum termination voltage should be identical to the device supply voltage.
(4) Compliant to SMBus 2.0 physical layer specification. See System Management Bus (SMBus) Specification Version 2.0, section 3.1.1 SMBus common AC specifications for details.
(5) Specified by Design. Parameter not tested in production.