ZHCSO34F April   2011  – August 2021 DS80PCI402

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings (1) (1) (1)
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Ratings
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Electrical Characteristics — Serial Management Bus Interface
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 15
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 4-Level Input Configuration Guidelines
    4. 8.4 Device Functional Modes
      1. 8.4.1 Pin Control Mode
      2. 8.4.2 SMBUS Mode
    5. 8.5 Programming
      1. 8.5.1 System Management Bus (SMBus) and Configuration Registers
      2. 8.5.2 Transfer of Data Through the SMBus
      3. 8.5.3 Writing a Register
      4. 8.5.4 Reading a Register
      5. 8.5.5 SMBus Controller Mode
    6. 8.6 Register Maps
      1.      31
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 3.3-V or 2.5-V Supply Mode Operation
    2. 10.2 Power Supply Bypassing
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 PCB Layout Considerations for Differential Pairs
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 接收文档更新通知
    2. 12.2 支持资源
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 术语表
  13. 13Mechanical, Packaging, and Orderable Information

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9.1 Application Information

In PCIe Gen-3 applications, the specification requires Rx-Tx link training to establish and optimize signal conditioning settings at 8 Gbps. In link training, the Rx partner requests a series of FIR - preshoot and de-emphasis coefficients (10 Presets) from the Tx partner. The Rx partner includes 7-levels (6 dB to 12 dB) of CTLE followed by a single tap DFE. The link training would pre-condition the signal with an equalized link between the root-complex and endpoint. Note that there is no link training in PCIe Gen-1 (2.5 Gbps) or PCIe Gen-2 (5.0 Gbps) applications. The DS80PCI402 is placed in between the Tx and Rx. It would help extend the PCB trace reach distance by boosting the attenuated signals with its equalization, so that the signal can be more easily recovered by the downstream Rx. In Gen 3 mode, DS80PCI402 transmit outputs are designed to pass the Tx Preset signaling onto the Rx for the PCIe Gen 3 link to train and optimize the equalization settings. The suggested setting for the DS80PCI402 are EQ=00, VOD = 1.2 Vp-p and DEM = 0 dB. Additional adjustments to increase the EQ or DEM setting should be performed to optimize the eye opening in the Rx partner. See the tables below for Pin mode and SMBus mode configurations.

Table 9-1 Suggested Device Settings in Pin Mode
CHANNELPIN MODE SETTINGS
EQx[1:0]0, 0 (Level 1)
DEMx[1:0]Float, R (Level 10)
Table 9-2 Suggested Device Settings in SMBus Reader MODE
REGISTERWRITE VALUECOMMENTS
0x060x18Enables SMBus Reader MODE Register Control
0x0F0x00Set CHB_0 EQ to 0x00.
0x100xADSet CHB_0 VOD to 101'b (1.2 Vp-p).
0x110x00Set CHB_0 DEM to 000'b (0 dB).
0x160x00Set CHB_1 EQ to 0x00.
0x170xADSet CHB_1 VOD to 101'b (1.2 Vp-p).
0x180x00Set CHB_1 DEM to 000'b (0 dB).
0x1D0x00Set CHB_2 EQ to 0x00.
0x1E0xADSet CHB_2 VOD to 101'b (1.2 Vp-p).
0x1F0x00Set CHB_2 DEM to 000'b (0 dB).
0x240x00Set CHB_3 EQ to 0x00.
0x250xADSet CHB_3 VOD to 101'b (1.2 Vp-p).
0x260x00Set CHB_3 DEM to 000'b (0 dB).
0x2C0x00Set CHA_0 EQ to 0x00.
0x2D0xADSet CHA_0 VOD to 101'b (1.2 Vp-p).
0x2E0x00Set CHA_0 DEM to 000'b (0 dB).
0x330x00Set CHA_1 EQ to 0x00.
0x340xADSet CHA_1 VOD to 101'b (1.2 Vp-p).
0x350x00Set CHA_1 DEM to 000'b (0 dB).
0x3A0x00Set CHA_2 EQ to 0x00.
0x3B0xADSet CHA_2 VOD to 101'b (1.2 Vp-p).
0x3C0x00Set CHA_2 DEM to 000'b (0 dB).
0x410x00Set CHA_3 EQ to 0x00.
0x420xADSet CHA_3 VOD to 101'b (1.2 Vp-p).
0x430x00Set CHA_3 DEM to 000'b (0 dB).