ZHCSTI6 October   2023 DS320PR410

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Electrical Characteristics
    6. 6.6 High Speed Electrical Characteristics
    7. 6.7 SMBUS/I2C Timing Charateristics
    8. 6.8 Typical Characteristics
    9. 6.9 Typical Jitter Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Linear Equalization
      2. 7.3.2 Flat-Gain
      3. 7.3.3 Receiver Detect State Machine
    4. 7.4 Device Functional Modes
      1. 7.4.1 Active PCIe Mode
      2. 7.4.2 Active Buffer Mode
      3. 7.4.3 Standby Mode
    5. 7.5 Programming
      1. 7.5.1 Pin mode
        1. 7.5.1.1 Five-Level Control Inputs
      2. 7.5.2 SMBUS/I2C Register Control Interface
        1. 7.5.2.1 Shared Registers
        2. 7.5.2.2 Channel Registers
      3. 7.5.3 SMBus/I 2 C Primary Mode Configuration (EEPROM Self Load)
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 PCIe Reach Extension – x16 Lane Configuration
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 接收文档更新通知
    2. 9.2 支持资源
    3. 9.3 Trademarks
    4. 9.4 静电放电警告
    5. 9.5 术语表
  11. 10Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.3.3 Receiver Detect State Machine

The DS320PR410 deploys an Rx detect state machine that governs the Rx detection cycle as defined in the PCI express specifications. At power up or after a manual PD toggle the redriver determines whether or not a valid PCI express termination is present at the far end receiver. The RX_DET pin of DS320PR410 provides additional flexibility for system designers to appropriately set the device in desired mode as provided in Table 7-3. If multiple DS320PR410 devices are used for a same PCI express link, then the PD pins from different devices can be shorted and driven together. For most applications the RX_DET pin can be left floating for default settings. In SMBus/I2C mode each channel can be configured independently.

Table 7-3 Receiver Detect State Machine Settings
PD RX_DET Rx Impedance COMMENTS
L L0 Always 50 Ω PCI Express Rx detection state machine is disabled. Recommended for non PCIe interface use case where the DS320PR410 is used as buffer with equalization.
L L1 Pre Detect: Hi-Z
Post Detect: 50 Ω.		 Outputs polls until 3 consecutive valid detections
L L2 Pre Detect: Hi-Z
Post Detect: 50 Ω.		 Outputs polls until 2 consecutive valid detections
L L3 NA Reserved
L L4 (Float) Pre Detect: Hi-Z
Post Detect: 50 Ω.		 Tx polls every ≅150 µs until valid termination is detected. Rx impedance held at Hi-Z until detection. Reset by asserting PD high for 200 µs then low.
H X Hi-Z Reset Channels 0-3 signal path and set their Rx impedance to Hi-Z

In PCIe applications, the PD pin can be connected to PCIe sideband signals PERST# with inverted polarity or one or more appropriate PRSNTx# signals to achieve the desired RX detect functionality.