ZHCSCK7A June   2014  – June 2014 DRV8802-Q1

PRODUCTION DATA.  

  1. 特性
  2. 应用
  3. 说明
  4. 修订历史记录
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Handling Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 PWM Motor Drivers
      2. 7.3.2 Bridge Control
      3. 7.3.3 Current Regulation
      4. 7.3.4 Decay Mode and Braking
      5. 7.3.5 Blanking Time
      6. 7.3.6 nRESET and nSLEEP Operation
      7. 7.3.7 Protection Circuits
        1. 7.3.7.1 Overcurrent Protection (OCP)
        2. 7.3.7.2 Thermal Shutdown (TSD)
        3. 7.3.7.3 Undervoltage Lockout (UVLO)
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Drive Current
        2. 8.2.2.2 Slow-Decay SR (Brake Mode)
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
    1. 9.1 Bulk Capacitance
    2. 9.2 Power Supply and Logic Sequencing
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Information
      1. 10.3.1 Thermal Protection
      2. 10.3.2 Power Dissipation
      3. 10.3.3 Heatsinking
  11. 11器件和文档支持
    1. 11.1 Trademarks
    2. 11.2 Electrostatic Discharge Caution
    3. 11.3 术语表
  12. 12机械封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

5 Pin Configuration and Functions

28-Pin HTSSOP With PowerPAD
PWP Package
Top View
po_pwp_slvsci2.gif

Pin Functions

PIN TYPE(1) DESCRIPTION EXTERNAL COMPONENTS
OR CONNECTIONS
NAME NO.
POWER AND GROUND
CP1 1 IO Charge pump flying capacitor Connect a 0.01-μF 50-V capacitor between CP1 and CP2.
CP2 2 IO Charge pump flying capacitor
GND 14 Device ground
28
V3P3OUT 15 O 3.3-V regulator output Bypass to GND with a 0.47-μF 6.3-V ceramic capacitor. Can be used to supply VREF.
VMA 4 Bridge A power supply Connect to motor supply (8 to 45 V). Both pins must be connected to same supply.
VMB 11 Bridge B power supply
VCP 3 IO High-side gate drive voltage Connect a 0.1-μF 16-V ceramic capacitor and a 1-MΩ resistor to VMx.
CONTROL
AI0 24 I Bridge A current set Sets bridge A current: 00 = 100%,
01 = 71%, 10 = 38%, 11 = 0
AI1 25 I
AENBL 21 I Bridge A enable Logic high to enable bridge A
APHASE 20 I Bridge A phase (direction) Logic high sets AOUT1 high, AOUT2 low
AVREF 12 I Bridge A current set reference input Reference voltage for winding current set. Can be driven individually with an external DAC for microstepping, or tied to a reference (for example, V3P3OUT).
BVREF 13 I Bridge B current set reference input
BI0 26 I Bridge B current set Sets bridge B current: 00 = 100%,
01 = 71%, 10 = 38%, 11 = 0
BI1 27 I
BENBL 22 I Bridge B enable Logic high to enable bridge B
BPHASE 23 I Bridge B phase (direction) Logic high sets BOUT1 high, BOUT2 low
DECAY 19 I Decay (brake) mode Low = brake (slow decay),
high = coast (fast decay)
nRESET 16 I Reset input Active-low reset input initializes internal logic and disables the H-bridge outputs
nSLEEP 17 I Sleep mode input Logic high to enable device, logic low to enter low-power sleep mode
STATUS
nFAULT 18 OD Fault Logic low when in fault condition (overtemperature, overcurrent)
OUTPUT
AOUT1 5 O Bridge A output 1 Connect to motor winding A
AOUT2 7 O Bridge A output 2
BOUT1 10 O Bridge B output 1 Connect to motor winding B
BOUT2 8 O Bridge B output 2
ISENA 6 IO Bridge A ground and current sense Connect to current sense resistor for bridge A
ISENB 9 IO Bridge B ground and current sense Connect to current sense resistor for bridge B
(1) I = input, O = output, OZ = tri-state output, OD = open-drain output, IO = input/output