ZHCSUL8 December   2023 DRV8334

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
    1. 5.1 Pin Functions 48-Pin DRV8334
  7. 6 Specification
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings DRV8334
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information DRV8334
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 SPI Timing Diagrams
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Three BLDC Gate Drivers
        1. 7.3.1.1 PWM Control Modes
          1. 7.3.1.1.1 6x PWM Mode
          2. 7.3.1.1.2 3x PWM Mode with INLx enable control
          3. 7.3.1.1.3 3x PWM Mode with SPI enable control
          4. 7.3.1.1.4 1x PWM Mode
          5. 7.3.1.1.5 SPI Gate Drive Mode
        2. 7.3.1.2 Gate Drive Architecture
          1. 7.3.1.2.1 Bootstrap diode
          2. 7.3.1.2.2 GVDD Charge pump
          3. 7.3.1.2.3 VCP Trickle Charge pump
          4. 7.3.1.2.4 Gate Driver Output
          5. 7.3.1.2.5 Passive and Semi-active pull-down resistor
          6. 7.3.1.2.6 TDRIVE Gate Drive Timing Control
          7. 7.3.1.2.7 Propagation Delay
          8. 7.3.1.2.8 Deadtime and Cross-Conduction Prevention
      2. 7.3.2 Low-Side Current Sense Amplifiers
        1. 7.3.2.1 Unidirectional Current Sense Operation
        2. 7.3.2.2 Bidirectional Current Sense Operation
      3. 7.3.3 Gate Driver Shutdown
        1. 7.3.3.1 DRVOFF Gate Driver Shutdown
        2. 7.3.3.2 Gate Driver Shutdown Timing Sequence
      4. 7.3.4 Gate Driver Protective Circuits
        1. 7.3.4.1  PVDD Supply Undervoltage Lockout (PVDD_UV)
        2. 7.3.4.2  GVDD Undervoltage Lockout (GVDD_UV)
        3. 7.3.4.3  BST Undervoltage Lockout (BST_UV)
        4. 7.3.4.4  MOSFET VDS Overcurrent Protection (VDS_OCP)
        5. 7.3.4.5  VSENSE Overcurrent Protection (SEN_OCP)
        6. 7.3.4.6  Phase Comparators
        7. 7.3.4.7  Thermal Shutdown (OTSD)
        8. 7.3.4.8  Thermal Warning (OTW)
        9. 7.3.4.9  OTP CRC
        10. 7.3.4.10 SPI Watchdog Timer
    4. 7.4 Device Functional Modes
      1. 7.4.1 Gate Driver Functional Modes
        1. 7.4.1.1 Sleep Mode
        2. 7.4.1.2 Operating Mode
      2. 7.4.2 Device Power Up Sequence
    5. 7.5 Programming
      1. 7.5.1 SPI
      2. 7.5.2 SPI Format
      3. 7.5.3 SPI Format Diagrams
    6. 7.6 Register Maps
      1. 7.6.1 STATUS Registers
      2. 7.6.2 CONTROL Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Typical Application with 48-pin package
        1. 8.2.1.1 External Components
      2. 8.2.2 Application Curves
  10. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Community Resources
    4. 10.4 Trademarks
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Package Option Addendum
    2. 11.2 Tape and Reel Information

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7.6.1 STATUS Registers

Table 7-7 lists the memory-mapped registers for the STATUS registers. All register offset addresses not listed in Table 7-7 should be considered as reserved locations and the register contents should not be modified.

Table 7-7 STATUS Registers
AddressAcronymRegister NameSection
0hIC_STAT1IC Status Register 1Section 7.6.1.1
1hIC_STAT2IC Status Register 2Section 7.6.1.2
2hIC_STAT3IC Status Register 3Section 7.6.1.3
3hIC_STAT4IC Status Register 4Section 7.6.1.4
4hIC_STAT5IC Status Register 5Section 7.6.1.5
5hIC_STAT6IC Status Register 6Section 7.6.1.6

Complex bit access types are encoded to fit into small table cells. Table 7-8 shows the codes that are used for access types in this section.

Table 7-8 STATUS Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Reset or Default Value
-nValue after reset or the default value

7.6.1.1 IC_STAT1 Register (Address = 0h) [Reset = 8000h]

IC_STAT1 is shown in Table 7-9.

Return to the Summary Table.

Table 7-9 IC_STAT1 Register Field Descriptions
BitFieldTypeResetDescription
15SPI_OKR1h No SPI Fault is detected
0b = SPI Fault is detected
1b = No fault
14FAULTR0h Logic OR of FAULT status registers. Mirrors nFAULT pin.
0b = nFAULT status logic-low
1b = nFAULT status logic-high. One or multiple fault events detected.
13WARNR0h Logic OR of WARN status, except OTW
0b = No warning event detected
1b = One or multiple warning event detected
12VDSR0h Logic OR of VDS overcurrent detection
0b = No VDS events detected.
1b = One or multiple VDS events detected.
11VGSR0h Logic OR of VGS detection
0b = No VGS events detected.
1b = One or multiple VGS events detected.
10SNS_OCPR0h Logic OR of Sense overcurrent detection
0b = No sense overcurrent events detected.
1b = One or multiple sense overcurrent events detected.
9OVR0h Logic OR of supply voltage overvoltage detection
0b = No overvoltage events detected.
1b = One or more overvoltage events detected.
8UVR0h Logic OR of supply voltage undervoltage detection
0b = No undervoltage events detected.
1b = One or more undervoltage events detected.
7-2RESERVEDR0h Reserved
1OTWR0h Overtemperature Warning Status Bit
0b = No event is detected
1b = Overtemperature warning event detected
0DRV_STATR0h Indicates Driver Enable Status. Mirrors ENABLE_DRV register bit

7.6.1.2 IC_STAT2 Register (Address = 1h) [Reset = 0000h]

IC_STAT2 is shown in Table 7-10.

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Table 7-10 IC_STAT2 Register Field Descriptions
BitFieldTypeResetDescription
15-11RESERVEDR0h Reserved
10SNS_OCP_AR0h Overcurrent on External Sense Resistor Status Bit on phase A
9SNS_OCP_BR0h Overcurrent on External Sense Resistor Status Bit on phase B
8SNS_OCP_CR0h Overcurrent on External Sense Resistor Status Bit on phase C
7-6RESERVEDR0h Reserved
5VDS_HAR0h VDS Overcurrent Status on the A High-side MOSFET
4VDS_LAR0h VDS Overcurrent Status on the A Low-side MOSFET
3VDS_HBR0h VDS Overcurrent Status on the B High-side MOSFET
2VDS_LBR0h VDS Overcurrent Status on the B Low-side MOSFET
1VDS_HCR0h VDS Overcurrent Status on the C High-side MOSFET
0VDS_LCR0h VDS Overcurrent Status on the C Low-side MOSFET

7.6.1.3 IC_STAT3 Register (Address = 2h) [Reset = 0000h]

IC_STAT3 is shown in Table 7-11.

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Table 7-11 IC_STAT3 Register Field Descriptions
BitFieldTypeResetDescription
15-6RESERVEDR0h Reserved
5VGS_HAR0h Gate driver fault status on the A High-side MOSFET.
4VGS_LAR0h Gate driver fault status on the A Low-side MOSFET.
3VGS_HBR0h Gate driver fault status on the B High-side MOSFET.
2VGS_LBR0h Gate driver fault status on the B Low-side MOSFET.
1VGS_HCR0h Gate driver fault status on the C High-side MOSFET.
0VGS_LCR0h Gate driver fault status on the C Low-side MOSFET.

7.6.1.4 IC_STAT4 Register (Address = 3h) [Reset = 0000h]

IC_STAT4 is shown in Table 7-12.

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Table 7-12 IC_STAT4 Register Field Descriptions
BitFieldTypeResetDescription
15PVDD_OVR0h PVDD overvoltage status
14PVDD_UVR0h PVDD undervoltage status
13VDRAIN_OVR0h VDRAIN overvoltage status
12VDRAIN_UVR0h VDRAIN undervoltage status
11VCP_OVR0h VCP overvoltage status
10VCP_UVR0h VCP undervoltage status
9GVDD_OVR0h GVDD overvoltage status
8GVDD_UVR0h GVDD undervoltage status
7RESERVEDR0h Reserved
6RESERVEDR0h Reserved
5BSTA_OVR0h BST overvoltage on the A High-side MOSFET
4BSTA_UVR0h BST undervoltage on the A High-side MOSFET
3BSTB_OVR0h BST overvoltage on the B High-side MOSFET
2BSTB_UVR0h BST undervoltage on the B High-side MOSFET
1BSTC_OVR0h BST overvoltage on the C High-side MOSFET
0BSTC_UVR0h BST undervoltage on the C High-side MOSFET

7.6.1.5 IC_STAT5 Register (Address = 4h) [Reset = 0000h]

IC_STAT5 is shown in Table 7-13.

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Table 7-13 IC_STAT5 Register Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR0h Reserved
14PVDD_UVWR0h PVDD undervoltage warning status
13-11RESERVEDR0h Reserved
10GVDD_CP_LDOR0h GVDD operating mode status
0b = Charge pump
1b = LDO mode
9OTSDR0h
8WDT_FLTR0h Watch dog timer fault bit
7SPI_CRC_FLTR0h SPI CRC fault bit
6SPI_ADDR_FLTR0h SPI Address fault bit
5SPI_CLK_FLTR0h SPI Clock Framing fault bit. For 32-bit frame (SPI_CRC_EN is 1), the SPI_CLK_FLT is set to 1 if the number of SPI clock of one SPI frame is 1 to 31, 33 or higher. The SPI_CLK_FLT is 0 if the number of SPI clock is 0 or 32.
4OTP_CRC_FLTR0h OTP CRC fault bit. A fault of OTP memory used for device production has been detected.
3RESERVEDR0h Reserved
2RESERVEDR0h Reserved
1STP_FLTR0h Shoot Through Protection violation
0DEADT_FLTR0h Dead time violation

7.6.1.6 IC_STAT6 Register (Address = 5h) [Reset = 0000h]

IC_STAT6 is shown in Table 7-14.

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Table 7-14 IC_STAT6 Register Field Descriptions
BitFieldTypeResetDescription
15PHCA_FLTR0h Indicates phase comparator fault of PHCA
14PHCB_FLTR0h Indicates phase comparator fault of PHCB
13PHCC_FLTR0h Indicates phase comparator fault of PHCC
12RESERVEDR0h Reserved
11VREF_OVR0h VREF input overvoltage status
10VREF_UVR0h VREF input undervoltage status
9VDDSDO_UVR0h Device internal regulator VDDSDO regulator undervoltage status
8RESERVEDR0h Reserved
7DVDD_OVR0h DVDD overvoltage status
6INT_REG_FLTR0h Internal regulator fault status
5-4RESERVEDR0h Reserved
3DEV_MODE_FLTR0h Device mode fault status
2-1RESERVEDR0h Reserved
0CLK_MON_FLTR0h Clock monitor fault status