ZHCSIG4B July   2018  – October 2020 DLPC3434

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1. 5.1 Test Pins and General Control
    2. 5.2 Parallel Port Input
    3. 5.3 DSI Input Data and Clock
    4. 5.4 DMD Reset and Bias Control
    5. 5.5 DMD Sub-LVDS Interface
    6. 5.6 Peripheral Interface
    7. 5.7 GPIO Peripheral Interface
    8. 5.8 Clock and PLL Support
    9. 5.9 Power and Ground
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Electrical Characteristics
    6. 6.6  Pin Electrical Characteristics
    7. 6.7  Internal Pullup and Pulldown Electrical Characteristics
    8. 6.8  DMD Sub-LVDS Interface Electrical Characteristics
    9. 6.9  DMD Low-Speed Interface Electrical Characteristics
    10. 6.10 System Oscillator Timing Requirements
    11. 6.11 Power Supply and Reset Timing Requirements
    12. 6.12 Parallel Interface Frame Timing Requirements
    13. 6.13 Parallel Interface General Timing Requirements
    14. 6.14 Flash Interface Timing Requirements
    15. 6.15 Other Timing Requirements
    16. 6.16 DMD Sub-LVDS Interface Switching Characteristics
    17. 6.17 DMD Parking Switching Characteristics
    18. 6.18 Chipset Component Usage Specification
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Source Requirements
        1. 7.3.1.1 Supported Resolution and Frame Rates
        2. 7.3.1.2 Parallel Interface Data Transfer Format
        3. 7.3.1.3 3D Display
      2. 7.3.2 Device Startup
      3. 7.3.3 SPI Flash
        1. 7.3.3.1 SPI Flash Interface
        2. 7.3.3.2 SPI Flash Programming
      4. 7.3.4 I2C Interface
      5. 7.3.5 Content Adaptive Illumination Control (CAIC)
      6. 7.3.6 Local Area Brightness Boost (LABB)
      7. 7.3.7 3D Glasses Operation
      8. 7.3.8 Test Point Support
      9. 7.3.9 DMD Interface
        1. 7.3.9.1 Sub-LVDS (HS) Interface
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
    1. 9.1 PLL Design Considerations
    2. 9.2 System Power-Up and Power-Down Sequence
    3. 9.3 Power-Up Initialization Sequence
    4. 9.4 DMD Fast Park Control (PARKZ)
    5. 9.5 Hot Plug I/O Usage
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 PLL Power Layout
      2. 10.1.2 Reference Clock Layout
        1. 10.1.2.1 Recommended Crystal Oscillator Configuration
      3. 10.1.3 Unused Pins
      4. 10.1.4 DMD Control and Sub-LVDS Signals
      5. 10.1.5 Layer Changes
      6. 10.1.6 Stubs
      7. 10.1.7 Terminations
      8. 10.1.8 Routing Vias
      9. 10.1.9 Thermal Considerations
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 第三方产品免责声明
      2. 11.1.2 Device Nomenclature
        1. 11.1.2.1 Device Markings
        2. 11.1.2.2 Video Timing Parameter Definitions
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Related Links
    4. 11.4 Receiving Notification of Documentation Updates
    5. 11.5 Support Resources
    6. 11.6 Trademarks
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
      1. 12.1.1 Packaging Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

5.9 Power and Ground

PINI/OTYPEDESCRIPTION
NAMENO.
VDDC5, D5, D7, D12, J4, J12, K3, L4, L12, M6, M9, D9, D13, F13, H13, L13, M10, D3, E3—PWRCore 1.1-V power (main 1.1 V)
VDDLP12C3—PWRReserved - tie to the VDD rail
VSSC4, D6, D8, D10, E4, E13, F4, G4, G12, H4, H12, J3, J13, K4, K12, L3, M4, M5, M8, M12, G13, C6, C8—GNDCore ground (eDRAM, DSI, I/O ground, thermal ground)
VCC18C7, C9, D4, E12, F12, K13, M11—PWRAll 1.8-V I/O power:
(1.8-V power supply for all I/O pins except the host or parallel interface and the SPI flash interface. This includes RESETZ, PARKZ, LED_SEL, CMP_OUT, GPIO, IIC1, TSTPT, and JTAG pins.)
VCC_INTFM3, M7, N3, N7—PWRHost or parallel interface I/O power: 1.8 V to 3.3 V (includes IIC0, PDATA, video syncs, and HOST_IRQ pins)
VCC_FLSHD11—PWRFlash interface I/O power: 1.8 V to 3.3 V
(dedicated SPI0 power pin)
VDD_PLLMH2—PWRMCG PLL (primary clock generator phase lock loop) 1.1-V power
VSS_PLLMG3—RTNMCG PLL return
VDD_PLLDJ2—PWRDCG PLL (DMD clock generator phase lock loop) 1.1-V power
VSS_PLLDH3—RTNDCG PLL return
Table 5-1 I/O Type Subscript Definition
I/OSUPPLY REFERENCEESD STRUCTURE
SUBSCRIPTDESCRIPTION
11.8-V LVCMOS I/O buffer with 8-mA driveVcc18ESD diode to GND and supply rail
21.8-V LVCMOS I/O buffer with 4-mA driveVcc18ESD diode to GND and supply rail
31.8-V LVCMOS I/O buffer with 24-mA driveVcc18ESD diode to GND and supply rail
41.8-V sub-LVDS output with 4-mA driveVcc18ESD diode to GND and supply rail
51.8-V, 2.5-V, 3.3-V LVCMOS with 4-mA driveVcc_INTFESD diode to GND and supply rail
61.8-V LVCMOS inputVcc18ESD diode to GND and supply rail
71.8-V, 2.5-V, 3.3-V I2C with 3-mA driveVcc_INTFESD diode to GND and supply rail
81.8-V I2C with 3-mA driveVcc18ESD diode to GND and supply rail
91.8-V, 2.5-V, 3.3-V LVCMOS with 8-mA driveVcc_INTFESD diode to GND and supply rail
10LVDS I/OVDD for high speed transmit, high speed receive, and low power receive.
VDDLP12 for low power transmit		ESD diode to GND and supply rail
111.8-V, 2.5-V, 3.3-V LVCMOS inputVcc_INTFESD diode to GND and supply rail
121.8-V, 2.5-V, 3.3-V LVCMOS inputVcc_FLSHESD diode to GND and supply rail
131.8-V, 2.5-V, 3.3-V LVCMOS with 8-mA driveVcc_FLSHESD diode to GND and supply rail