ZHCSLO2E October 2020 – January 2021 DAC5652
PRODUCTION DATA
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| Timing - Dual Bus Mode | ||||||
| tsu | Input setup time | 1 | ns | |||
| th | Input hold time | 1 | ns | |||
| tLPH | Input clock pulse high time | 1 | ns | |||
| tLAT | Clock latency (WRTA/B to outputs) | 4 | 4 | clk | ||
| tPD | Propagation delay time | 1.5 | ns | |||
| Timing - Single Bus Interleaved Mode | ||||||
| tsu | Input setup time | 0.5 | ns | |||
| th | Input hold time | 0.5 | ns | |||
| tLAT | Clock latency (WRTA/B to outputs) | 4 | 4 | clk | ||
| tPD | Propagation delay time | 1.5 | ns | |||