ZHCSOP0B October 2001 – January 2022 CDCVF25081
PRODUCTION DATA
请参考 PDF 数据表获取器件具体的封装图。
PIN | I/O TYPE(1) | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
INPUT CLOCK | |||
CLKIN | 1 | I | Clock input. CLKIN must have a fixed frequency and phase in order for the PLL to acquire lock. Once the circuit is powered up and a valid signal is applied, a stabilization time is required for the PLL to phase lock the feedback signal to CLKIN. |
INPUT SELECT | |||
S1, S2 | 9, 8 | I | Input Selection. Selects input port. (See Table 8-2.) |
FEEDBACK | |||
FBIN | 16 | I | Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be wired to one of the outputs to complete the feedback loop of the internal PLL. The integrated PLL synchronizes the FBIN and output signal so there is nominally zero-delay from input clock to output clock. |
OUTPUT CLOCKS | |||
1Y0 | 2 | O | Bank 1 Y0 clock output with an integrated 25-Ω series-damping resistor. |
1Y1 | 3 | O | Bank 1 Y1 clock output with an integrated 25-Ω series-damping resistor. |
1Y2 | 14 | O | Bank 1 Y2 clock output with an integrated 25-Ω series-damping resistor. |
1Y3 | 15 | O | Bank 1 Y3 clock output with an integrated 25-Ω series-damping resistor. |
2Y0 | 6 | O | Bank 2 Y0 clock output with an integrated 25-Ω series-damping resistor. |
2Y1 | 7 | O | Bank 2 Y1 clock output with an integrated 25-Ω series-damping resistor. |
2Y2 | 10 | O | Bank 2 Y2 clock output with an integrated 25-Ω series-damping resistor. |
2Y3 | 11 | O | Bank 2 Y3 clock output with an integrated 25-Ω series-damping resistor. |
SUPPLY VOLTAGE AND GROUND | |||
VDD | 4, 13 | P | 3.3V power supply for output channels and core voltage. |
GND | 5, 12 | G | Ground. Connect ground pad to system ground. |