ZHCSFP6A November   2016  – January 2017 CDCLVP111-SP

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用范围
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 LVECL DC Electrical Characteristics
    6. 6.6 LVPECL DC Electrical Characteristics
    7. 6.7 AC Electrical Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Fanout Buffer for Line Card Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 LVPECL Output Termination
          2. 8.2.1.2.2 Input Termination
        3. 8.2.1.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Power-Supply Filtering
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 接收文档更新通知
    2. 11.2 社区资源
    3. 11.3 商标
    4. 11.4 静电放电警告
    5. 11.5 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

5 Pin Configuration and Functions

HFG Package
36-Pin CFP
Top View

Pin Functions(1)

PIN TYPE DESCRIPTION
NAME NO.
CLK_SEL 2 Input Clock select. Used to select between CLK0 and CLK1 input pairs. LVTTL/LVCMOS functionality compatible.
CLK0, CLK0 3, 4 Input Differential LVECL/LVPECL input pair.
CLK1, CLK1 6, 7 Input
Q[9:0] 12, 14, 16, 20, 22, 24, 26, 30, 32, 34 Output LVECL/LVPECL clock outputs, these outputs provide low-skew copies of CLKn.
Q[9:0] 11, 13, 15, 19, 21, 23, 25, 29, 31, 33 Output LVECL/LVPECL complementary clock outputs, these outputs provide copies of CLKn.
VBB 5 Power Reference voltage output for single-ended input operation.
VCC 1, 9, 10, 17, 18, 27, 28, 35, 36 Power Supply voltage.
VEE 8 Power Device ground or negative supply voltage in ECL mode.
(1) CLKn, CLK_SEL pull down resistor = 75 kΩ; CLKn pull up resistor = 37.5 kΩ; CLKn pull down resistor = 50 kΩ.