ZHCSM61C November   2014  – September 2020 CC3200MOD

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Functional Block Diagrams
  5. 5 Revision History
  6. 6 Device Comparison
    1. 6.1 Related Products
  7. 7 Terminal Configuration and Functions
    1. 7.1 CC3200MOD Pin Diagram
    2. 7.2 Pin Attributes
      1. 7.2.1 Module Pin Attributes
    3. 7.3 Pin Attributes and Pin Multiplexing
    4. 7.4 Recommended Pin Multiplexing Configurations
      1. 7.4.1 ADC Reference Accuracy Specifications
    5. 7.5 Drive Strength and Reset States for Analog-Digital Multiplexed Pins
    6. 7.6 Pad State After Application of Power to Chip, but Before Reset Release
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Power-On Hours (POH)
    4. 8.4  Recommended Operating Conditions
    5. 8.5  Power Consumption Summary
      1. 8.5.1 Current Consumption
    6. 8.6  Brownout and Blackout Conditions
    7. 8.7  WLAN RF Characteristics
      1. 8.7.1 WLAN Receiver Characteristics
      2. 8.7.2 WLAN Transmitter Characteristics
    8. 8.8  Reset Requirement
    9. 8.9  Thermal Resistance Characteristics for MOB and MON Packages
    10. 8.10 Timing and Switching Characteristics
      1. 8.10.1 nRESET
      2. 8.10.2 Wake Up From Hibernate Timing
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Arm® Cortex®-M4 处理器内核子系统
    4. 9.4 CC3200 Device Encryption
    5. 9.5 Wi-Fi® Network Processor Subsystem
    6. 9.6 Power-Management Subsystem
      1. 9.6.1 VBAT Wide-Voltage Connection
    7. 9.7 Low-Power Operating Mode
    8. 9.8 Memory
      1. 9.8.1 External Memory Requirements
      2. 9.8.2 Internal Memory
        1. 9.8.2.1 SRAM
        2. 9.8.2.2 ROM
        3. 9.8.2.3 Memory Map
    9. 9.9 Boot Modes
      1. 9.9.1 Overview
      2. 9.9.2 Invocation Sequence and Boot Mode Selection
      3. 9.9.3 Boot Mode List
  10. 10Applications, Implementation, and Layout
    1. 10.1 Device Connection and Layout Fundamentals
      1. 10.1.1 Power Supply Decoupling and Bulk Capacitors
      2. 10.1.2 Reset
      3. 10.1.3 Unused Pins
      4. 10.1.4 General Layout Recommendations
      5. 10.1.5 Do's and Don'ts
    2. 10.2 Reference Schematics
    3. 10.3 Design Requirements
    4. 10.4 Detailed Design Procedure
    5. 10.5 Layout Recommendations
      1. 10.5.1 RF Section (Placement and Routing)
      2. 10.5.2 Antenna Placement and Routing
      3. 10.5.3 Transmission Line
  11. 11Environmental Requirements and Specifications
    1. 11.1 PCB Bending
    2. 11.2 Handling Environment
      1. 11.2.1 Terminals
      2. 11.2.2 Falling
    3. 11.3 Storage Condition
      1. 11.3.1 Moisture Barrier Bag Before Opened
      2. 11.3.2 Moisture Barrier Bag Open
    4. 11.4 Baking Conditions
    5. 11.5 Soldering and Reflow Condition
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
      2. 12.1.2 Firmware Updates
    2. 12.2 Device Nomenclature
    3. 12.3 Documentation Support
    4. 12.4 Trademarks
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Mechanical Drawing
    2. 13.2 Package Option
      1. 13.2.1 Packaging Information
      2. 13.2.2 Tape and Reel Information

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • MOB|63
散热焊盘机械数据 (封装 | 引脚)

9.3 Arm® Cortex®-M4 处理器内核子系统

高性能 Arm® Cortex®-M4 处理器是一个低成本平台，可满足减少存储器和引脚数以及降低功耗的需求，同时提供出色的计算性能和系统中断响应能力。

  • Cortex®-M4 内核的低延迟中断处理具有以下特性：
    • 32 位 Arm®Thumb® 指令集针对嵌入式应用进行了优化
    • 处理程序和线程模式
    • 在进入和退出期间处理器状态自动保存和恢复，实现低延迟中断处理
    • 支持 ARMv6 未对齐的访问
  • 嵌套矢量中断控制器 (NVIC) 与处理器内核紧密集成，可实现低延迟中断处理。NVIC 包含以下特性：
    • 可配置的优先级位（从 3 到 8）
    • 动态重设中断优先级
    • 优先级分组，支持选择优先中断级别和非优先中断级别
    • 支持尾链和中断延迟到达，执行背对背中断处理时，两次中断之间无状态保存和恢复开销
    • 中断到达时自动保存处理器状态，中断退出时恢复，无指令开销
    • 唤醒中断控制器 (WIC) 提供超低功耗睡眠模式支持
  • 总线接口：
    • 先进的高性能总线 (AHB-Lite) 接口：系统总线接口
    • 对存储器和部分外设的位段支持，包含原子位段写入和读取操作
  • 低成本调试解决方案的特性：
    • 对系统中所有存储器和寄存器进行调试访问，包括对存储器映射器件的访问，内核暂停时对内部内核寄存器的访问和在 SYSRESETn 置位时对调试控制寄存器的访问
    • 串行线调试端口 (SW-DP) 或串行线 JTAG 调试端口 (SWJ-DP) 调试访问
    • 闪存补丁和断点 (FPB) 单元，可实施断点和代码补丁