SLUSCU2 November   2017

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (Continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power-Up from Battery Without DC Source
      2. 8.3.2 Power-Up From DC Source
        1. 8.3.2.1 CHRG_OK Indicator
        2. 8.3.2.2 Input Voltage and Current Limit Setup
        3. 8.3.2.3 Battery Cell Configuration
        4. 8.3.2.4 Device Hi-Z State
      3. 8.3.3 Converter Operation
        1. 8.3.3.1 Inductor Setting through IADPT Pin
        2. 8.3.3.2 Continuous Conduction Mode (CCM)
        3. 8.3.3.3 Pulse Frequency Modulation (PFM)
      4. 8.3.4 Current and Power Monitor
        1. 8.3.4.1 High-Accuracy Current Sense Amplifier (IADPT and IBAT)
        2. 8.3.4.2 High-Accuracy Power Sense Amplifier (PSYS)
      5. 8.3.5 Input Source Dynamic Power Manage
      6. 8.3.6 Two-Level Adapter Current Limit (Peak Power Mode)
      7. 8.3.7 Processor Hot Indication
        1. 8.3.7.1 PROCHOT During Low Power Mode
        2. 8.3.7.2 PROCHOT Status
      8. 8.3.8 Device Protection
        1. 8.3.8.1 Watchdog Timer
        2. 8.3.8.2 Input Overvoltage Protection (ACOV)
        3. 8.3.8.3 Input Overcurrent Protection (ACOC)
        4. 8.3.8.4 System Overvoltage Protection (SYSOVP)
        5. 8.3.8.5 Battery Overvoltage Protection (BATOVP)
        6. 8.3.8.6 Battery Short
        7. 8.3.8.7 Thermal Shutdown (TSHUT)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Forward Mode
        1. 8.4.1.1 System Voltage Regulation with Narrow VDC Architecture
        2. 8.4.1.2 Battery Charging
    5. 8.5 Programming
      1. 8.5.1 SMBus Interface
        1. 8.5.1.1 SMBus Write-Word and Read-Word Protocols
        2. 8.5.1.2 Timing Diagrams
    6. 8.6 Register Map
      1. 8.6.1  Setting Charge and PROCHOT Options
        1. 8.6.1.1 ChargeOption0 Register (SMBus address = 12h) [reset = E20Eh]
        2. 8.6.1.2 ChargeOption1 Register (SMBus address = 30h) [reset = 211h]
        3. 8.6.1.3 ChargeOption2 Register (SMBus address = 31h) [reset = 2B7]
        4. 8.6.1.4 ChargeOption3 Register (SMBus address = 32h) [reset = 0h]
        5. 8.6.1.5 ProchotOption0 Register (SMBus address = 33h) [reset = 04A54h]
        6. 8.6.1.6 ProchotOption1 Register (SMBus address = 34h) [reset = 8120h]
        7. 8.6.1.7 ADCOption Register (SMBus address = 35h) [reset = 2000h]
      2. 8.6.2  Charge and PROCHOT Status
        1. 8.6.2.1 ChargerStatus Register (SMBus address = 20h) [reset = 0000h]
        2. 8.6.2.2 ProchotStatus Register (SMBus address = 21h) [reset = 0h]
      3. 8.6.3  ChargeCurrent Register (SMBus address = 14h) [reset = 0h]
        1. 8.6.3.1 Battery Pre-Charge Current Clamp
      4. 8.6.4  MaxChargeVoltage Register (SMBus address = 15h) [reset value based on CELL_BATPRESZ pin setting]
      5. 8.6.5  MinSystemVoltage Register (SMBus address = 3Eh) [reset value based on CELL_BATPRESZ pin setting]
        1. 8.6.5.1 System Voltage Regulation
      6. 8.6.6  Input Current and Input Voltage Registers for Dynamic Power Management
        1. 8.6.6.1 Input Current Registers
          1. 8.6.6.1.1 IIN_HOST Register With 10-mΩ Sense Resistor (SMBus address = 3Fh) [reset = 4000h]
          2. 8.6.6.1.2 IIN_DPM Register With 10-mΩ Sense Resistor (SMBus address = 022h) [reset = 0h]
          3. 8.6.6.1.3 InputVoltage Register (SMBus address = 3Dh) [reset = VBUS-1.28V]
      7. 8.6.7  ADCVBUS/PSYS Register (SMBus address = 23h)
      8. 8.6.8  ADCIBAT Register (SMBus address = 24h)
      9. 8.6.9  ADCIINCMPIN Register (SMBus address = 25h)
      10. 8.6.10 ADCVSYSVBAT Register (SMBus address = 26h) (reset = )
      11. 8.6.11 ID Registers
        1. 8.6.11.1 ManufactureID Register (SMBus address = FEh) [reset = 0040h]
        2. 8.6.11.2 Device ID (DeviceAddress) Register (SMBus address = FFh) [reset = 0h]
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 ACP-ACN Input Filter
        2. 9.2.2.2 Inductor Selection
        3. 9.2.2.3 Input Capacitor
        4. 9.2.2.4 Output Capacitor
        5. 9.2.2.5 Power MOSFETs Selection
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
      1. 11.2.1 Layout Consideration of Current Path
      2. 11.2.2 Layout Consideration of Short Circuit Protection
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)(2)
MIN MAX UNIT
Voltage SRN, SRP, ACN, ACP, VBUS, VSYS, BATDRV –0.3 30 V
SW1, SW2 –2.0 30
BTST1, BTST2, HIDRV1, HIDRV2 –0.3 36
LODRV1, LODRV2 (25 ns) –4.0 7
HIDRV1, HIDRV2 (25 ns) –4.0 36
SW1, SW2 (25 ns) –4.0 30
SDA, SCL, REGN, CHRG_OK, CELL_BATPRESZ, ILIM_HIZ, LODRV1, LODRV2, VDDA, COMP1, COMP2, CMPIN, CMPOUT –0.3 7
PROCHOT –0.3 5.5
IADPT, IBAT, PSYS –0.3 3.6
Differential voltage BTST1-SW1, BTST2-SW2, HIDRV1-SW1, HIDRV2-SW2 –0.3 7 V
SRP-SRN, ACP-ACN –0.5 0.5
Junction temperature range, TJ –40 155 °C
Storage temperature, Tstg –40 155 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to GND if not specified. Currents are positive into, negative out of the specified terminal. Consult Packaging Section of the data book for thermal limitations and considerations of packages.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
Voltage ACN, ACP, VBUS 0 24 V
SRN, SRP, VSYS, BATDRV 0 19.2
SW1, SW2 –2 24
BTST1, BTST2, HIDRV1, HIDRV2 0 30
SDA, SCL, REGN, CHRG_OK, CELL_BATPRESZ, ILIM_HIZ, LODRV1, LODRV2, VDDA, COMP1, COMP2, CMPIN, CMPOUT 0 6.5
PROCHOT 0 5.3
IADPT, IBAT, PSYS 0 3.3
Differential voltage BTST1-SW1, BTST2-SW2, HIDRV1-SW1, HIDRV2-SW2 0 6.5 V
SRP-SRN, ACP-ACN –0.35 0.35
Junction temperature, TJ –40 125 °C
Operating free-air temperature, TA –40 85 °C

7.4 Thermal Information

THERMAL METRIC(1) bq25708 UNIT
RSN (WQFN)
32 PINS
RθJA Junction-to-ambient thermal resistance 37.2 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 26.1 °C/W
RθJB Junction-to-board thermal resistance 7.8 °C/W
ψJT Junction-to-top characterization parameter 0.3 °C/W
ψJB Junction-to-board characterization parameter 7.8 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 2.3 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VINPUT_OP Input voltage operating range 3.5 26 V
REGULATION ACCURACY
MAX SYSTEM VOLTAGE REGULATION
VSYSMAX_RNG System voltage regulation, measured on VSYS 1.024 19.2 V
VSYSMAX_ACC System voltage regulation accuracy (charge disable) REG0x15() = 0x41A0H (16.800 V) VSRN + 160 mV V
–2% 2%
REG0x15() = 0x3130H (12.592 V) VSRN + 160 mV V
–2% 2%
REG0x15() = 0x20D0H (8.400 V) VSRN + 160 mV V
–3% 3%
REG0x15() = 0x1060H (4.192 V) VSRN + 160 mV V
–3% 3%
MINIMUM SYSTEM VOLTAGE REGULATION
VSYSMIN_RNG System voltage regulation, measured on VSYS 1.024 19.2 V
VSYSMIN_REG_ACC Minimum system voltage regulation accuracy (charge enable, VBAT below REG0x3E() setting) REG0x3E() = 0x3000H 12.288 V
–2% 2%
REG0x3E() = 0x2400H 9.216 V
–2% 2%
REG0x3E() = 0x1800H 6.144 V
–3% 3%
REG0x3E() = 0x0E00H 3.584 V
–3% 4%
CHARGE VOLTAGE REGULATION
VBAT_RNG Battery voltage regulation 1.024 19.2 V
VBAT_REG_ACC Battery voltage regulation accuracy (charge enable) (0°C to 85°C) REG0x15() = 0x41A0H 16.8 V
–0.5% 0.5%
REG0x15() = 0x3130H 12.592 V
–0.5% 0.5%
REG0x15() = 0x20D0H 8.4 V
–0.6% 0.6%
REG0x15() = 0x1060H 4.192 V
–1.1% 1.2%
CHARGE CURRENT REGULATION IN FAST CHARGE
VIREG_CHG_RNG Charge current regulation differential voltage range VIREG_CHG = VSRP – VSRN 0 81.28 mV
ICHRG_REG_ACC Charge current regulation accuracy 10-mΩ current sensing resistor, VBAT above 0x3E() setting (0°C to 85°C) REG0x14() = 0x1000H 4096 mA
–3% 2%
REG0x14() = 0x0800H 2048 mA
–4% 3%
REG0x14() = 0x0400H 1024 mA
–5% 5%
REG0x14() = 0x0200H 512 mA
–12% 12%
CHARGE CURRENT REGULATION IN LDO MODE
ICLAMP Pre-charge current clamp CELL 2s-4s 384 mA
CELL 1 s, VSRN < 3 V 384 mA
CELL 1 s, 3 V < VSRN < VSYS_MIN 2 A
IPRECHRG_REG_ACC Pre-charge current regulation accuracy with 10-mΩ SRP/SRN series resistor, VBAT below REG0x3E() setting (0°C to 85°C) REG0x14() = 0x0180H 384 mA
2S-4S –15% 15%
1S –25% 25%
REG0x14() = 0x0100H 256 mA
2S-4S –20% 20%
1S –35% 35%
REG0x14() = 0x00C0H 192 mA
2S-4S –25% 25%
1S –50% 50%
REG0x14() = 0x0080H 128 mA
2S-4S –30% 30%
ILEAK_SRP_SRN SRP, SRN leakage current mismatch (0°C to 85°C) –12 –10 µA
INPUT CURRENT REGULATION
VIREG_DPM_RNG Input current regulation differential voltage range VIREG_DPM = VACP – VACN 0.5 64 mV
IDPM_REG_ACC Input current regulation accuracy with 10-mΩ ACP/ACN series resistor (–40°C to 105°C) REG0x3F() = 0x4FFFH 3820 4000 mA
REG0x3F() = 0x3BFFH 2830 3000 mA
REG0x3F() = 0x1DFFH 1350 1500 mA
REG0x3F() = 0x09FFH 340 500 mA
ILEAK_ACP_ACN ACP, ACN leakage current mismatch –16 10 µA
VIREG_DPM_RNG_ILIM Voltage Range for input current regulation 1 4 V
IDPM_REG_ACC_ILIM Input Current Regulation Accuracy on ILIM_HIZ pin VILIM_HIZ = 1 V + 40 × IDPM × RAC, with 10-mΩ ACP/ACN series resistor VILIM_HIZ = 2.6 V 3800 4000 4200 mA
VILIM_HIZ = 2.2 V 2800 3000 3200 mA
VILIM_HIZ = 1.6 V 1300 1500 1700 mA
VILIM_HIZ = 1.2 V 300 500 700 mA
ILEAK_ILIM ILIM_HIZ pin leakage –1 1 µA
INPUT VOLTAGE REGULATION
VIREG_DPM_RNG Input voltage regulation range Voltage on VBUS 3.2 19.52 V
VDPM_REG_ACC Input voltage regulation accuracy REG0x3D()=0x3C80H 18688 mV
–2% 2%
REG0x3D()=0x1E00H 10880 mV
–2.5% 2.5%
REG0x3D()=0x0500H 4480 mV
–3% 5%
REFERENCE AND BUFFER
REGN REGULATOR
VREGN_REG REGN regulator voltage (0 mA–60 mA) VVBUS = 10 V 5.7 6 6.3 V
VDROPOUT REGN voltage in drop out mode VVBUS = 5 V, ILOAD = 20 mA 3.8 4.3 4.6 V
IREGN_LIM_Charging REGN current limit when converter is enabled VVBUS = 10 V, force VREGN = 4 V 50 65 mA
CREGN REGN output capacitor required for stability ILOAD = 100 µA to 50 mA 2.2 µF
CVDDA REGN output capacitor required for stability ILOAD = 100 µA to 50 mA 1 µF
QUIESCENT CURRENT
IBAT_BATFET_ON System powered by battery. BATFET on. ISRN + ISRP + ISW2+ IBTST2 + ISW1 + IBTST1+ ACP + IACN + IVBUS + IVSYS VBAT = 18 V, REG0x12[15] = 1, in low power mode 22 45 µA
VBAT = 18 V, REG0x12[15] = 1, in low power mode, REG0x30[14:13] = 01, REGN off 105 175 µA
VBAT=18 V, REG0x12[15] = 1, in low power mode, REG0x30[14:13]= 10, REGN off 60 90 µA
VBAT = 18 V, REG0x12[15] = 0, REG0x30[12] = 0, REGN on, EN_PSYS 860 1150 µA
VBAT = 18 V, REG0x12[15] = 0, REG0x30[12] = 1, REGN on 960 1250
IAC_SW_LIGHT_buck Input current during PFM in buck mode, no load, IVBUS + IACP + IACN + IVSYS + ISRP + ISRN + ISW1 + IBTST + ISW2 + IBTST2 VIN = 20 V, VBAT = 12.6 V, 3 s, REG0x12[10] = 0; MOSFET Qg = 4 nC 2.2 mA
IAC_SW_LIGHT_boost Input current during PFM in boost mode, no load, IVBUS + IACP + IACN + IVSYS + ISRP + ISRN + ISW1 + IBTST2 + ISW2 + IBTST2 VIN = 5 V, VBAT = 8.4 V, 2 s, REG0x12[10] = 0; MOSFET Qg = 4 nC 2.7 mA
IAC_SW_LIGHT_buckboost Input current during PFM in buck boost mode, no load, IVBUS + IACP + IACN + IVSYS + ISRP + ISRN + ISW1 + IBTST1 + ISW2 + IBTST2 VIN = 12 V, VBAT = 12 V, REG0x12[10] = 0; MOSFET Qg = 4 nC 2.4 mA
VACP/N_OP Input common mode range Voltage on ACP/ACN 3.8 26 V
VIADPT_CLAMP IADPT output clamp voltage 3.1 3.2 3.3 V
IIADPT IADPT output current 1 mA
AIADPT Input current sensing gain V(IADPT) / V(ACP-ACN), REG0x12[4] = 0 20 V/V
V(IADPT) / V(ACP-ACN), REG0x12[4] = 1 40 V/V
VIADPT_ACC Input current monitor accuracy V(ACP-ACN) = 40.96 mV –2% 2%
V(ACP-ACN) = 20.48 mV –3% 3%
V(ACP-ACN) =10.24 mV –6% 6%
V(ACP-ACN) = 5.12 mV –10% 10%
CIADPT_MAX Maximum output load capacitance 100 pF
VSRP/N_OP Battery common mode range Voltage on SRP/SRN 2.5 18 V
VIBAT_CLAMP IBAT output clamp voltage 3.1 3.2 3.3 V
IIBAT IBAT output current 1 mA
AIBAT Charge and discharge current sensing gain on IBAT pin V(IBAT) / V(SRN-SRP), REG0x12[3] = 0, 8 V/V
V(IBAT) / V(SRN-SRP), REG0x12[3] = 1, 16 V/V
IIBAT_CHG_ACC Charge and discharge current monitor accuracy on IBAT pin V(SRN-SRP) = 40.96 mV –2% 2%
V(SRN-SRP) = 20.48 mV –3% 4%
V(SRN-SRP) =10.24 mV –6% 6%
V(SRN-SRP) = 5.12 mV –12% 12%
CIBAT_MAX Maximum output load capacitance 100 pF
SYSTEM POWER SENSE AMPLIFIER
VPSYS PSYS output voltage range 0 3.3 V
IPSYS PSYS output current 0 160 µA
APSYS PSYS system gain V(PSYS) / (P(IN)+ P(BAT)), REG0x30[9] = 1 1 µA/W
VPSYS_ACC PSYS gain accuracy (REG0x3B[9] = 1), TA = 25°C Adapter only with system power = 19.5 V / 45 W –5% 5%
Battery only with system power 11 V / 44 W (25°C) –5% 5%
VPSYS_CLAMP PSYS clamp voltage 3 3.3 V
COMPARATOR
VBUS UNDER VOLTAGE LOCKOUT COMPARATOR
VVBUS_UVLOZ VBUS undervoltage rising threshold VBUS rising 2.34 2.55 2.77 V
VVBUS_UVLO VBUS undervoltage falling threshold VBUS falling 2.2 2.4 2.6 V
VVBUS_UVLO_HYST VBUS undervoltage hysteresis 150 mV
VVBUS_CONVEN VBUS converter enable rising threshold VBUS rising 3.2 3.5 3.9 V
VVBUS_CONVENZ VBUS converter enable falling threshold VBUS falling 2.9 3.2 3.5 V
VVBUS_CONVEN_HYST VBUS converter enable hysteresis 400 mV
BATTERY UNDER VOLTAGE LOCKOUT COMPARATOR
VVBAT_UVLOZ VBAT undervoltage rising threshold VSRN rising 2.35 2.55 2.75 V
VVBAT_UVLO VBAT undervoltage falling threshold VSRN falling 2.2 2.4 2.6 V
VVBAT_UVLO_HYST VBAT undervoltage hysteresis 150 mV
BATTERY LOWV COMPARATOR (Pre-charge to Fast Charge Thresold for 1S)
VBATLV_FALL BATLOWV falling threshold 1 s 2.80 V
VBATLV_RISE BATLOWV rising threshold 3.00 V
VBATLV_RHYST BATLOWV hysteresis 200 mV
INPUT OVER-VOLTAGE COMPARATOR (ACOVP)
VACOV_RISE VBUS overvoltage rising threshold VBUS rising 25 26 27 V
VACOV_FALL VBUS overvoltage falling threshold VBUS falling 24 24.5 25 V
VACOV_HYST VBUS overvoltage hysteresis 1.5 V
tACOV_RISE_DEG VBUS overvoltage rising deglitch VBUS rising to stop converter 100 µs
tACOV_FALL_DEG VBUS overvoltage falling deglitch VBUS falling to start converter 1 ms
INPUT OVER CURRENT COMPARATOR (ACOC)
VACOC ACP to ACN rising threshold, w.r.t. ILIM2 in REG0x33[15:11] Voltage across input sense resistor rising, Reg0x31[2] = 1 195% 210% 225%
VACOC_FLOOR Measure between ACP and ACN Set IDPM to minimum 44 50 56 mV
VACOC_CEILING Measure between ACP and ACN Set IDPM to maximum 172 180 188 mV
tACOC_DEG_RISE Rising deglitch time Deglitch time to trigger ACOC 250 µs
tACOC_RELAX Relax time Relax time before converter starts again 250 ms
SYSTEM OVER-VOLTAGE COMPARATOR (SYSOVP)
VSYSOVP_RISE System overvoltage rising threshold to turn off converter 1 s 4.85 5 5.1 V
2 s 11.7 12 12.2 V
3s 18 18.5 19 V
VSYSOVP_FALL System overvoltage falling threshold 1 s 4.8 V
2 s 11.5 V
3s 18 V
ISYSOVP Discharge current when SYSOVP stop switching was triggered on SYS 20 mA
BAT OVER-VOLTAGE COMPARATOR (BATOVP)
VBATOVP_RISE Overvoltage rising threshold as percentage of VBAT_REG in REG0x15() 1 s, 4.2 V 102.5% 104% 105.7%
2 s - 4 s 102.5% 104% 105%
VBATOVP_FALL Overvoltage falling threshold as percentage of VBAT_REG in REG0x15() 1 s 100% 102% 104%
2 s - 4 s 100% 102% 103%
VBATOVP_HYST Overvoltage hysteresis as percentage of VBAT_REG in REG0x15() 1 s 2%
2 s - 4 s 2%
IBATOVP Discharge current during BATOVP on SRP and SRN 20 mA
tBATOVP_RISE Overvoltage rising deglitch to turn off BATDRV to disable charge 20 ms
CONVERTER OVER-CURRENT COMPARATOR (Q2)
VOCP_limit_Q2 Converter Over-Current Limit Reg0x31[5]=1 150 mV
Reg0x31[5]=0 210
VOCP_limit_SYSSHORT_Q2 System Short or SRN<2.5 V Reg0x31[5]=1 45 mV
Reg0x31[5]=0 60
CONVERTER OVER-CURRENT COMPARATOR (ACX)
VOCP_limit_ACX Converter Over-Current Limit Reg0x31[4]=1 150 mV
Reg0x31[4]=0 280
VOCP_limit_SYSSHORT_ ACX System Short or SRN<2.5 V Reg0x31[4]=1 90 mV
Reg0x31[4]=0 150
THERMAL SHUTDOWN COMPARATOR
TSHUT_RISE Thermal shutdown rising temperature Temperature increasing 155 °C
TSHUTF_FALL Thermal shutdown falling temperature Temperature reducing 135 °C
TSHUT_HYS Thermal shutdown hysteresis 20 °C
tSHUT_RDEG Thermal shutdown rising deglitch 100 µs
tSHUT_FHYS Thermal shutdown falling deglitch 12 ms
VSYS PROCHOT COMPARATOR
VSYS_PROCHOT VSYS threshold falling threshold Reg0x36[7:6] = 00, 1 s 2.85 V
Reg0x36[7:6] = 00, 2–4 s 5.75 V
Reg0x36[7:6] = 01, 1 s 2.95 3.1 3.25 V
Reg0x36[7:6] = 01, 2–4 s 5.8 5.95 6.1 V
Reg0x36[7:6] = 10, 1 s 3.3 V
Reg0x36[7:6] = 10, 2–4 s 6.25 V
Reg0x36[7:6] = 11, 1 s 3.5 V
Reg0x36[7:6] = 11, 2–4 s 6.5 V
tSYS_PRO_RISE_DEG VSYS rising deglitch for throttling 8 µs
ICRIT PROCHOT COMPARATOR
VICRIT_PRO Input current rising threshold for throttling as percentage above ILIM2 (REG0x33[15:11]) Reg0x36[15:11] = 00000 105% 110% 116%
Reg0x36[15:11] = 01001 142% 150% 155%
Reg0x36[15:11] = 11110 410% 430% 455%
INOM PROCHOT COMPARATOR
VINOM_PRO INOM rising threshold as percentage of IIN (REG0x3F()) 105% 110% 116%
IDCHG PROCHOT COMPARATOR
VIDCHG_PRO IDCHG threshold for throttling for IDSCHG of 6 A Reg0x38 [15:10]=001100 6144 mA
95% 102%
INDEPENDENT COMPARATOR
VINDEP_CMP Independent comparator threshold Reg0x30[7] = 1, CMPIN falling 1.17 1.2 1.23 V
Reg0x30[7] = 0, CMPIN falling 2.27 2.3 2.33 V
VINDEP_CMP_HYS Independent comparator hysteresis Reg0x06[6] = 0, CMPIN falling 100 mV
POWER MOSFET DRIVER
PWM OSCILLATOR AND RAMP
FSW PWM switching frequency Reg0x00[9] = 0 1020 1200 1380 kHz
Reg0x00[9] = 1 680 800 920 kHz
BATFET GATE DRIVER (BATDRV)
VBATDRV_ON Gate drive voltage on BATFET 8.5 10 11.5 V
VBATDRV_DIODE Drain-source voltage on BATFET during ideal diode operation 30 mV
RBATDRV_ON Measured by sourcing 10-µA current to BATDRV 3 4 6 kΏ
RBATDRV_OFF Measured by sinking 10-µA current from BATDRV 1.2 2.1 kΏ
PWM HIGH SIDE DRIVER (HIDRV Q1)
RDS_HI_ON_Q1 High side driver (HSD) turnon resistance VBTST1 – VSW1 = 5 V 6 Ω
RDS_HI_OFF_Q1 High side driver turnoff resistance VBTST1 – VSW1 = 5 V 1.3 2.2 Ω
VBTST1_REFRESH Bootstrap refresh comparator falling threshold voltage VBTST1 – VSW1 when low side refresh pulse is requested 3.2 3.7 4.6 V
PWM HIGH SIDE DRIVER (HIDRV Q4)
RDS_HI_ON_Q4 High side driver (HSD) turnon resistance VBTST2 – VSW2 = 5 V 6 Ω
RDS_HI_OFF_Q4 High side driver turnoff resistance VBTST2 – VSW2 = 5 V 1.5 2.4 Ω
VBTST2_REFRESH Bootstrap refresh comparator falling threshold voltage VBTST2 – VSW2 when low side refresh pulse is requested 3.3 3.7 4.6 V
PWM LOW SIDE DRIVER (LODRV Q2)
RDS_LO_ON_Q2 Low side driver (LSD) turnon resistance VBTST1 – VSW1 = 5.5 V 6 Ω
RDS_LO_OFF_Q2 Low side driver turnoff resistance VBTST1 – VSW1 = 5.5 V 1.7 2.6 Ω
PWM LOW SIDE DRIVER (LODRV Q3)
RDS_LO_ON_Q3 Low side driver (LSD) turnon resistance VBTST2 – VSW2 = 5.5 V 7.6 Ω
RDS_LO_OFF_Q3 Low side driver turnoff resistance VBTST2 – VSW2 = 5.5 V 2.9 4.6 Ω
INTERNAL SOFT START During Charge Enable
SSSTEP_DAC Soft Start Step Size 64 mA
SSSTEP_DAC Soft Start Step Time 8 µs
INTEGRATED BTST DIODE (D1)
VF_D1 Forward bias voltage IF = 20 mA at 25°C 0.8 V
VR_D1 Reverse breakdown voltage IR = 2 µA at 25°C 20 V
INTEGRATED BTST DIODE (D2)
VF_D2 Forward bias voltage IF = 20 mA at 25°C 0.8 V
VR_D2 Reverse breakdown voltage IR = 2 µA at 25°C 20 V
PWM DRIVERS TIMING
INTERFACE
LOGIC INPUT (SDA, SCL)
VIN_ LO Input low threshold SMBus 0.8 V
VIN_ HI Input high threshold SMBus (bq25708) 2.1 V
LOGIC OUTPUT OPEN DRAIN (SDA, CHRG_OK, CMPOUT)
VOUT_ LO Output saturation voltage 5-mA drain current 0.4 V
VOUT_ LEAK Leakage current V = 7 V –1 1 mA
LOGIC OUTPUT OPEN DRAIN SDA
VOUT_ LO_SDA Output Saturation Voltage 5 mA drain current 0.4 V
VOUT_ LEAK_SDA Leakage Current V = 7V –1 1 mA
LOGIC OUTPUT OPEN DRAIN CHRG_OK
VOUT_ LO_CHRG_OK Output Saturation Voltage 5 mA drain current 0.4 V
VOUT_ LEAK _CHRG_OK Leakage Current V = 7V –1 1 mA
LOGIC OUTPUT OPEN DRAIN CMPOUT
VOUT_ LO_CMPOUT Output Saturation Voltage 5 mA drain current 0.4 V
VOUT_ LEAK _CMPOUT Leakage Current V = 7V –1 1 mA
LOGIC OUTPUT OPEN DRAIN (PROCHOT)
VOUT_ LO_PROCHOT Output saturation voltage 50-Ω pullup to 1.05 V / 5-mA load 300 mV
VOUT_ LEAK_PROCHOT Leakage current V = 5.5 V –1 1 mA
ANALOG INPUT (ILIM_HIZ)
VHIZ_ LO Voltage to get out of HIZ mode ILIM_HIZ pin rising 0.8 V
VHIZ_ HIGH Voltage to enable HIZ mode ILIM_HIZ pin falling 0.4 V
ANALOG INPUT (CELL_BATPRESZ)
VCELL_4S 4S REGN = 6 V, as percentage of REGN 68.4% 75%
VCELL_3S 3s REGN = 6 V, as percentage of REGN 51.7% 55% 65%
VCELL_2S 2S REGN = 6 V, as percentage of REGN 35% 40% 49.1%
VCELL_1S 1S REGN = 6 V, as percentage of REGN 18.4% 25% 31.6%
VCELL_BATPRESZ_RISE Battery is present 18%
VCELL_BATPRESZ_FALL Battery is removed CELL_BATPRESZ falling 15%
ANALOG INPUT (COMP1, COMP2)
ILEAK_COMP1 COMP1 Leakage –120 120 nA
ILEAK_COMP2 COMP2 Leakage –120 120 nA

7.6 Timing Requirements

MIN TYP MAX UNIT
SMBus TIMING CHARACTERISTICS
tr SCLK/SDATA rise time 1 µs
tf SCLK/SDATA fall time 300 ns
tW(H) SCLK pulse width high 4 50 µs
tW(L) SCLK Pulse Width Low 4.7 µs
tSU(STA) Setup time for START condition 4.7 µs
tH(STA) START condition hold time after which first clock pulse is generated 4 µs
tSU(DAT) Data setup time 250 µs
tH(DTA) Data hold time 300 µs
tSU(STOP) Setup time for STOP condition 4 µs
t(BUF) Bus free time between START and STOP condition 4.7 µs
FS(CL) Clock Frequency 10 100 KHz
HOST COMMUNICATION FAILURE
ttimeout SMBus bus release timeout(1) 25 35 ms
tBOOT Deglitch for watchdog reset signal 10 ms
tWDI Watchdog timeout period, ChargeOption() bit [14:13] = 01(2) 35 44 53 s
Watchdog timeout period, ChargeOption() bit [14:13] = 10(2) 70 88 105 s
Watchdog timeout period, ChargeOption() bit [14:13] = 11(2) (default) 140 175 210 s
(1) Devices participating in a transfer will timeout when any clock low exceeds the 25ms minimum timeout period. Devices that have detected a timeout condition must reset the communication no later than the 35 ms maximum timeout period. Both a master and a slave must adhere to the maximum value specified as it incorporates the cumulative stretch limit for both a master (10 ms) and a slave (25 ms).
(2) User can adjust threshold via SMBus ChargeOption() REG0x12.

7.7 Typical Characteristics

bq25708 D001_SLUSCP0.gif
VIN = 5 V
Figure 1. Light Load Efficiency
bq25708 D003_SLUSCP0.gif
VIN = 20 V
Figure 3. Light Load Efficiency
bq25708 D005_SLUSCP0.gif
VIN = 9 V
Figure 5. System Efficiency
bq25708 D007_SLUSCP0.gif
VIN = 20 V
Figure 7. System Efficiency
bq25708 D002_SLUSCP0.gif
VIN = 12 V
Figure 2. Light Load Efficiency
bq25708 D004_SLUSCP0.gif
VIN = 5 V
Figure 4. System Efficiency
bq25708 D006_SLUSCP0.gif
VIN = 12 V
Figure 6. System Efficiency