SLUSCU2 November   2017

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (Continued)
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power-Up from Battery Without DC Source
      2. 8.3.2 Power-Up From DC Source
        1. 8.3.2.1 CHRG_OK Indicator
        2. 8.3.2.2 Input Voltage and Current Limit Setup
        3. 8.3.2.3 Battery Cell Configuration
        4. 8.3.2.4 Device Hi-Z State
      3. 8.3.3 Converter Operation
        1. 8.3.3.1 Inductor Setting through IADPT Pin
        2. 8.3.3.2 Continuous Conduction Mode (CCM)
        3. 8.3.3.3 Pulse Frequency Modulation (PFM)
      4. 8.3.4 Current and Power Monitor
        1. 8.3.4.1 High-Accuracy Current Sense Amplifier (IADPT and IBAT)
        2. 8.3.4.2 High-Accuracy Power Sense Amplifier (PSYS)
      5. 8.3.5 Input Source Dynamic Power Manage
      6. 8.3.6 Two-Level Adapter Current Limit (Peak Power Mode)
      7. 8.3.7 Processor Hot Indication
        1. 8.3.7.1 PROCHOT During Low Power Mode
        2. 8.3.7.2 PROCHOT Status
      8. 8.3.8 Device Protection
        1. 8.3.8.1 Watchdog Timer
        2. 8.3.8.2 Input Overvoltage Protection (ACOV)
        3. 8.3.8.3 Input Overcurrent Protection (ACOC)
        4. 8.3.8.4 System Overvoltage Protection (SYSOVP)
        5. 8.3.8.5 Battery Overvoltage Protection (BATOVP)
        6. 8.3.8.6 Battery Short
        7. 8.3.8.7 Thermal Shutdown (TSHUT)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Forward Mode
        1. 8.4.1.1 System Voltage Regulation with Narrow VDC Architecture
        2. 8.4.1.2 Battery Charging
    5. 8.5 Programming
      1. 8.5.1 SMBus Interface
        1. 8.5.1.1 SMBus Write-Word and Read-Word Protocols
        2. 8.5.1.2 Timing Diagrams
    6. 8.6 Register Map
      1. 8.6.1  Setting Charge and PROCHOT Options
        1. 8.6.1.1 ChargeOption0 Register (SMBus address = 12h) [reset = E20Eh]
        2. 8.6.1.2 ChargeOption1 Register (SMBus address = 30h) [reset = 211h]
        3. 8.6.1.3 ChargeOption2 Register (SMBus address = 31h) [reset = 2B7]
        4. 8.6.1.4 ChargeOption3 Register (SMBus address = 32h) [reset = 0h]
        5. 8.6.1.5 ProchotOption0 Register (SMBus address = 33h) [reset = 04A54h]
        6. 8.6.1.6 ProchotOption1 Register (SMBus address = 34h) [reset = 8120h]
        7. 8.6.1.7 ADCOption Register (SMBus address = 35h) [reset = 2000h]
      2. 8.6.2  Charge and PROCHOT Status
        1. 8.6.2.1 ChargerStatus Register (SMBus address = 20h) [reset = 0000h]
        2. 8.6.2.2 ProchotStatus Register (SMBus address = 21h) [reset = 0h]
      3. 8.6.3  ChargeCurrent Register (SMBus address = 14h) [reset = 0h]
        1. 8.6.3.1 Battery Pre-Charge Current Clamp
      4. 8.6.4  MaxChargeVoltage Register (SMBus address = 15h) [reset value based on CELL_BATPRESZ pin setting]
      5. 8.6.5  MinSystemVoltage Register (SMBus address = 3Eh) [reset value based on CELL_BATPRESZ pin setting]
        1. 8.6.5.1 System Voltage Regulation
      6. 8.6.6  Input Current and Input Voltage Registers for Dynamic Power Management
        1. 8.6.6.1 Input Current Registers
          1. 8.6.6.1.1 IIN_HOST Register With 10-mΩ Sense Resistor (SMBus address = 3Fh) [reset = 4000h]
          2. 8.6.6.1.2 IIN_DPM Register With 10-mΩ Sense Resistor (SMBus address = 022h) [reset = 0h]
          3. 8.6.6.1.3 InputVoltage Register (SMBus address = 3Dh) [reset = VBUS-1.28V]
      7. 8.6.7  ADCVBUS/PSYS Register (SMBus address = 23h)
      8. 8.6.8  ADCIBAT Register (SMBus address = 24h)
      9. 8.6.9  ADCIINCMPIN Register (SMBus address = 25h)
      10. 8.6.10 ADCVSYSVBAT Register (SMBus address = 26h) (reset = )
      11. 8.6.11 ID Registers
        1. 8.6.11.1 ManufactureID Register (SMBus address = FEh) [reset = 0040h]
        2. 8.6.11.2 Device ID (DeviceAddress) Register (SMBus address = FFh) [reset = 0h]
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 ACP-ACN Input Filter
        2. 9.2.2.2 Inductor Selection
        3. 9.2.2.3 Input Capacitor
        4. 9.2.2.4 Output Capacitor
        5. 9.2.2.5 Power MOSFETs Selection
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
      1. 11.2.1 Layout Consideration of Current Path
      2. 11.2.2 Layout Consideration of Short Circuit Protection
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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Layout

Layout Guidelines

The switching node rise and fall times should be minimized for minimum switching loss. Proper layout of the components to minimize high frequency current path loop (see Layout Example section) is important to prevent electrical and magnetic field radiation and high frequency resonant problems. Here is a PCB layout priority list for proper layout. Layout PCB according to this specific order is essential.

  1. Place the input capacitor as close as possible to the supply of the switching MOSFET and ground connections. Use a short copper trace connection. These parts must be placed on the same layer of PCB using vias to make this connection.
  2. The device must be placed close to the gate pins of the switching MOSFET. Keep the gate drive signal traces short for a clean MOSFET drive. The device can be placed on the other side of the PCB of switching MOSFETs.
  3. Place an inductor input pin as close as possible to the output pin of the switching MOSFET. Minimize the copper area of this trace to lower electrical and magnetic field radiation but make the trace wide enough to carry the charging current. Do not use multiple layers in parallel for this connection. Minimize parasitic capacitance from this area to any other trace or plane.
  4. The charging current sensing resistor should be placed right next to the inductor output. Route the sense leads connected across the sensing resistor back to the device in same layer, close to each other (minimize loop area) and do not route the sense leads through a high-current path (see Figure 50 for Kelvin connection for best current accuracy). Place a decoupling capacitor on these traces next to the device.
  5. Place an output capacitor next to the sensing resistor output and ground.
  6. Output capacitor ground connections must be tied to the same copper that connects to the input capacitor ground before connecting to system ground.
  7. Use a single ground connection to tie the charger power ground to the charger analog ground. Just beneath the device, use analog ground copper pour but avoid power pins to reduce inductive and capacitive noise coupling.
  8. Route analog ground separately from power ground. Connect analog ground and connect power ground separately. Connect analog ground and power ground together using power pad as the single ground connection point. Or using a 0-Ω resistor to tie analog ground to power ground (power pad should tie to analog ground in this case if possible).
  9. Decoupling capacitors must be placed next to the device pins. Make trace connection as short as possible.
  10. It is critical that the exposed power pad on the backside of the device package be soldered to the PCB ground.
  11. The via size and number should be enough for a given current path. See the EVM design (SLUUBG6) for the recommended component placement with trace and via locations. For the WQFN information, see SLUA271.

Layout Example

Layout Consideration of Current Path

bq25708 hi_f_path_lusa79.gif Figure 49. High Frequency Current Path

Layout Consideration of Short Circuit Protection

bq25708 sens_res_layout_lusa79.gif Figure 50. Sensing Resistor PCB Layout