ZHCSGA3A march   2017  – march 2023 BQ25601

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 说明（续）
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Power-On-Reset (POR)
      2. 9.3.2 Device Power Up from Battery without Input Source
      3. 9.3.3 Power Up from Input Source
        1. 9.3.3.1 Power Up REGN Regulation
        2. 9.3.3.2 Poor Source Qualification
        3. 9.3.3.3 Input Source Type Detection
          1. 9.3.3.3.1 PSEL Pins Sets Input Current Limit in BQ25601
        4. 9.3.3.4 Input Voltage Limit Threshold Setting (VINDPM Threshold)
        5. 9.3.3.5 Converter Power Up
      4. 9.3.4 Boost Mode Operation From Battery
      5. 9.3.5 Host Mode and Standalone Power Management
        1. 9.3.5.1 Host Mode and Default Mode in BQ25601
      6. 9.3.6 Power Path Management
      7. 9.3.7 Battery Charging Management
        1. 9.3.7.1 Autonomous Charging Cycle
        2. 9.3.7.2 Battery Charging Profile
        3. 9.3.7.3 Charging Termination
        4. 9.3.7.4 Thermistor Qualification
        5. 9.3.7.5 JEITA Guideline Compliance During Charging Mode
        6. 9.3.7.6 Boost Mode Thermistor Monitor During Battery Discharge Mode
        7. 9.3.7.7 Charging Safety Timer
      8. 9.3.8 Protections
        1. 9.3.8.1 Voltage and Current Monitoring in Converter Operation
          1. 9.3.8.1.1 Voltage and Current Monitoring in Buck Mode
            1. 9.3.8.1.1.1 Input Overvoltage (ACOV)
            2. 9.3.8.1.1.2 System Overvoltage Protection (SYSOVP)
        2. 9.3.8.2 Voltage and Current Monitoring in Boost Mode
          1. 9.3.8.2.1 VBUS Soft Start
          2. 9.3.8.2.2 VBUS Output Protection
          3. 9.3.8.2.3 Boost Mode Overvoltage Protection
        3. 9.3.8.3 Thermal Regulation and Thermal Shutdown
          1. 9.3.8.3.1 Thermal Protection in Buck Mode
          2. 9.3.8.3.2 Thermal Protection in Boost Mode
        4. 9.3.8.4 Battery Protection
          1. 9.3.8.4.1 Battery Overvoltage Protection (BATOVP)
          2. 9.3.8.4.2 Battery Overdischarge Protection
          3. 9.3.8.4.3 System Overcurrent Protection
    4. 9.4 Device Functional Modes
      1. 9.4.1 Narrow VDC Architecture
      2. 9.4.2 Dynamic Power Management
      3. 9.4.3 Supplement Mode
      4. 9.4.4 Shipping Mode and QON Pin
        1. 9.4.4.1 BATFET Disable Mode (Shipping Mode)
        2. 9.4.4.2 BATFET Enable (Exit Shipping Mode)
        3. 9.4.4.3 BATFET Full System Reset
        4. 9.4.4.4 QON Pin Operations
      5. 9.4.5 Status Outputs ( PG, STAT, INT )
        1. 9.4.5.1 Power Good Indicator ( PG Pin and PG_STAT Bit)
        2. 9.4.5.2 Charging Status Indicator (STAT)
        3. 9.4.5.3 Interrupt to Host ( INT)
    5. 9.5 Programming
      1. 9.5.1 Serial Interface
        1. 9.5.1.1 Data Validity
        2. 9.5.1.2 START and STOP Conditions
        3. 9.5.1.3 Byte Format
        4. 9.5.1.4 Acknowledge (ACK) and Not Acknowledge (NACK)
        5. 9.5.1.5 Target Address and Data Direction Bit
        6. 9.5.1.6 Single Read and Write
        7. 9.5.1.7 Multi-Read and Multi-Write
    6. 9.6 Register Maps
      1. 9.6.1  REG00
      2. 9.6.2  REG01
      3. 9.6.3  REG02
      4. 9.6.4  REG03
      5. 9.6.5  REG04
      6. 9.6.6  REG05
      7. 9.6.7  REG06
      8. 9.6.8  REG07
      9. 9.6.9  REG08
      10. 9.6.10 REG09
      11. 9.6.11 REG0A
      12. 9.6.12 REG0B
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Inductor Selection
        2. 10.2.2.2 Input Capacitor
        3. 10.2.2.3 Output Capacitor
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 第三方产品免责声明
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 接收文档更新通知
    4. 13.4 支持资源
    5. 13.5 Trademarks
    6. 13.6 静电放电警告
    7. 13.7 术语表
  14. 14Mechanical, Packaging, and Orderable Information

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机械数据 (封装 | 引脚)
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订购信息

7 Pin Configuration and Functions

GUID-CA24D9B6-DD07-4A17-8CAC-DC2CC341E651-low.gifFigure 7-1 RTW Package24-Pin WQFNTop View
Table 7-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME NO.
BAT 13 P Battery connection point to the positive terminal of the battery pack. The internal BATFET and current sensing is connected between SYS and BAT. Connect a 10 µF close to the BAT pin.
14
BTST 21 P PWM high side driver positive supply. Internally, the BTST pin is connected to the cathode of the boost-strap diode. Connect the 0.047-μF bootstrap capacitor from SW to BTST.
CE 9 DI Charge enable pin. When this pin is driven low, battery charging is enabled.
GND 17 P Ground.
18
INT 7 DO Open-drain interrupt Output. Connect the INT to a logic rail through 10-kΩ resistor. The INT pin sends an active low, 256-µs pulse to host to report charger device status and fault.
NC 8 — No Connect. Keep the pins float.
10
PG 3 DO Open drain active low power good indicator. Connect to the pull up rail through 10-kΩ resistor. LOW indicates a good input source if the input voltage is between UVLO and ACOV, above SLEEP mode threshold, and current limit is above 30 mA.
PMID 23 DO Connected to the drain of the reverse blocking MOSFET (RBFET) and the drain of HSFET. Put 10 μF ceramic capacitor on PMID to GND.
PSEL 2 DI Power source selection input. Set 500 mA input current limit by pulling this pin high and set 2.4A input current limit by pulling this pin low. Once the device gets into host mode, the host can program different input current limits to IINDPM register.
QON 12 DI BATFET enable/reset control input. When BATFET is in ship mode, a logic low of tSHIPMODE duration turns on BATFET to exit shipping mode. When VBUS is not plugged in, a logic low of tQON_RST (minimum 8 s) duration resets SYS (system power) by turning BATFET off for tBATFET_RST (minimum 250 ms) and then re-enable BATFET to provide full system power reset. The pin contains an internal 200-kΩ pull-up to maintain default high logic.
REGN 22 P LSFET driver and internal supply output. Internally, REGN is connected to the anode of the boost-strap diode. Connect a 4.7-μF (10-V rating) ceramic capacitor from REGN to GND. The capacitor should be placed close to the IC.
SCL 5 DI I2C interface clock. Connect SCL to the logic rail through a 10-kΩ resistor.
SDA 6 DIO I2C interface data. Connect SDA to the logic rail through a 10-kΩ resistor.
STAT 4 DO Open-drain charge status output. Connect the STAT pin to a logic rail via 10-kΩ resistor. The STAT pin indicates charger status. Collect a current limit resister and a LED from a rail to this pin.
Charge in progress: LOW
Charge complete or charger in SLEEP mode: HIGH
Charge suspend (fault response): 1-Hz, 50% duty cycle Pulses
This pin can be disabled via EN_ICHG_MON[1:0] register bits.
SW 19 P Switching node output. Connected to output inductor. Connect the 0.047-μF bootstrap capacitor from SW to BTST.
20
SYS 15 P Converter output connection point. The internal current sensing network is connected between SYS and BAT. Connect a 20 µF capacitor close to the SYS pin.
16
TS 11 AI Temperature qualification voltage input to support JEITA profile. Connect a negative temperature coefficient thermistor. Program temperature window with a resistor divider from REGN to TS to GND. Charge suspends when TS pin is out of range. When TS pin is not used, connect a 10-kΩ resistor from REGN to TS and connect a 10-kΩ resistor from TS to GND. It is recommended to use a 103AT-2 thermistor.
VAC 1 AI Charge input voltage sense. This pin must be connected to VBUS pin.
VBUS 24 P Charger input. The internal n-channel reverse block MOSFET (RBFET) is connected between VBUS and PMID pins. Place a 1-uF ceramic capacitor from VBUS to GND close to device.
Thermal Pad — P Thermal pad and ground reference. This pad is ground reference for the device and it is also the thermal pad used to conduct heat from the device. This pad should be tied externally to a ground plane through PCB vias under the pad.
(1) AI = Analog input, AO = Analog Output, AIO = Analog input Output, DI = Digital input, DO = Digital Output, DIO = Digital input Output, P = Power