ZHCSEJ2A November   2015  – January 2016

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 说明 （续）
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Device Power Up
        1. 8.3.1.1 Power-On-Reset (POR)
        2. 8.3.1.2 Power Up from Battery without DC Source
          1. 8.3.1.2.1 BATFET Turn Off
          2. 8.3.1.2.2 Shipping Mode
        3. 8.3.1.3 Power Up from DC Source
          1. 8.3.1.3.1 REGN LDO
          2. 8.3.1.3.2 Input Source Qualification
          3. 8.3.1.3.3 Input Current Limit Detection
          4. 8.3.1.3.4 PSEL/OTG Pins Set Input Current Limit
          5. 8.3.1.3.5 HIZ State with 100 mA USB Host
          6. 8.3.1.3.6 Force Input Current Limit Detection
        4. 8.3.1.4 Converter Power-Up
        5. 8.3.1.5 Boost Mode Operation from Battery
      2. 8.3.2 Power Path Management
        1. 8.3.2.1 Narrow VDC Architecture
        2. 8.3.2.2 Dynamic Power Management
        3. 8.3.2.3 Supplement Mode
      3. 8.3.3 Battery Charging Management
        1. 8.3.3.1 Autonomous Charging Cycle
        2. 8.3.3.2 Battery Charging Profile
        3. 8.3.3.3 Thermistor Qualification
          1. 8.3.3.3.1 Cold/Hot Temperature Window
        4. 8.3.3.4 Charging Termination
          1. 8.3.3.4.1 Termination When REG02[0] = 1
        5. 8.3.3.5 Charging Safety Timer
          1. 8.3.3.5.1 Safety Timer Configuration Change
        6. 8.3.3.6 USB Timer When Charging from USB100 mA Source
      4. 8.3.4 Status Outputs (PG, STAT, and INT)
        1. 8.3.4.1 Power Good Indicator (PG)
        2. 8.3.4.2 Charging Status Indicator (STAT)
        3. 8.3.4.3 Interrupt to Host (INT)
      5. 8.3.5 Protections
        1. 8.3.5.1 Input Current Limit on ILIM
        2. 8.3.5.2 Thermal Regulation and Thermal Shutdown
        3. 8.3.5.3 Voltage and Current Monitoring in Buck Mode
          1. 8.3.5.3.1 Input Over Voltage (ACOV)
          2. 8.3.5.3.2 System Over Voltage Protection (SYSOVP)
        4. 8.3.5.4 Voltage and Current Monitoring in Boost Mode
          1. 8.3.5.4.1 Over Current Protection
          2. 8.3.5.4.2 VBUS Over Voltage Protection
        5. 8.3.5.5 Battery Protection
          1. 8.3.5.5.1 Battery Over-Voltage Protection (BATOVP)
          2. 8.3.5.5.2 Battery Short Protection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Host Mode and Default Mode
        1. 8.4.1.1 Plug in USB100 mA Source with Good Battery
        2. 8.4.1.2 USB Timer When Charging from USB100 mA Source
    5. 8.5 Programming
      1. 8.5.1 Serial Interface
        1. 8.5.1.1 Data Validity
        2. 8.5.1.2 START and STOP Conditions
        3. 8.5.1.3 Byte Format
        4. 8.5.1.4 Acknowledge (ACK) and Not Acknowledge (NACK)
        5. 8.5.1.5 Slave Address and Data Direction Bit
          1. 8.5.1.5.1 Single Read and Write
          2. 8.5.1.5.2 Multi-Read and Multi-Write
    6. 8.6 Register Map
      1. 8.6.1 I2C Registers
        1. 8.6.1.1  Input Source Control Register REG00 [reset = 00110xxx, or 3x]
        2. 8.6.1.2  Power-On Configuration Register REG01 [reset = 00011011, or 0x1B]
        3. 8.6.1.3  Charge Current Control Register REG02 [reset = 01100000, or 60]
        4. 8.6.1.4  Pre-Charge/Termination Current Control Register REG03 [reset = 00010001, or 0x11]
        5. 8.6.1.5  Charge Voltage Control Register REG04 [reset = 10110010, or 0xB2]
        6. 8.6.1.6  Charge Termination/Timer Control Register REG05 [reset = 10011100, or 0x9C]
        7. 8.6.1.7  Boost Voltage/Thermal Regulation Control Register REG06 [reset = 01110011, or 0x73]
        8. 8.6.1.8  Misc Operation Control Register REG07 [reset = 01001011, or 4B]
        9. 8.6.1.9  System Status Register REG08
        10. 8.6.1.10 New Fault Register REG09
        11. 8.6.1.11 Vender / Part / Revision Status Register REG0A
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Inductor Selection
        2. 9.2.2.2 Input Capacitor
        3. 9.2.2.3 Output Capacitor
      3. 9.2.3 Application Performance Plots
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 器件支持
      1. 12.1.1 相关文档　
    2. 12.2 社区资源
    3. 12.3 商标
    4. 12.4 静电放电警告
    5. 12.5 Glossary
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7 Specifications

7.1 Absolute Maximum Ratings(1)

MIN MAX UNIT
Voltage
(with respect to GND)		 VBUS (converter not switching) –2 15(2) V
PMID (converter not switching) –0.3 15(2) V
STAT –0.3 12 V
BTST –0.3 12 V
SW –2 7
8 (Peak for 20ns duration)		 V
BAT, SYS (converter not switching) –0.3 6 V
SDA, SCL, INT, OTG, ILIM, REGN, TS, QON, CE PSEL –0.3 7 V
BTST TO SW –0.3 7 V
PGND to GND –0.3 0.3 V
Output sink current INT, STAT, PG 6 mA
Junction temperature –40 150 °C
Storage temperature range, Tstg –65 150 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to the network ground pin unless otherwise noted.
(2) VBUS is specified up to 16 V for a maximum of 24 hours under no load conditions.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1000 V
Charged device model (CDM), per JEDEC specification JESD22-C101(2) ±250 V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

MIN MAX UNIT
VIN Input voltage 3.9 6.2(1) V
ISYS Output current (SYS) 3.5 A
VBAT Battery voltage 4.4 V
IBAT Fast charging current 2 A
Discharging current with internal MOSFET 5.5 A
TA Operating free-air temperature range –40 85 °C
(1) The inherent switching noise voltage spikes should not exceed the absolute maximum rating on either the BTST or SW pins. A tight layout minimizes switching noise.

7.4 Thermal Information

THERMAL METRIC(1) bq24259 UNIT
RGE (VQFN)
24 PIN
RθJA Junction-to-ambient thermal resistance 32.2 °C/W
RθJCtop Junction-to-case (top) thermal resistance 29.8
RθJB Junction-to-board thermal resistance 9.1
ψJT Junction-to-top characterization parameter 0.3
ψJB Junction-to-board characterization parameter 9.1
RθJCbot Junction-to-case (bottom) thermal resistance 2.2
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report (SPRA953).

7.5 Electrical Characteristics

V(VBUS_UVLOZ) < V(VBUS) < V(ACOV) and V(VBUS) > V(BAT) + V(SLEEP), TJ = –40°C to 125°C and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
QUIESCENT CURRENTS
I(BAT) Battery discharge current (BAT, SW, SYS) V(VBUS) < V(UVLO), V(BAT) = 4.2 V, leakage between BAT and VBUS 5 µA
High-Z Mode, or no VBUS, BATFET disabled (REG07[5] = 1), –40°C – 85°C 16 20 µA
High-Z Mode, or no VBUS, BATFET enabled (REG07[5] = 0), –40°C – 85°C 32 55 µA
I(VBUS) Input supply current (VBUS) V(VBUS) = 5 V, High-Z mode, No battery 15 30 µA
V(VBUS) > V(UVLO), V(VBUS) > V(BAT), converter not switching 1.5 3 mA
V(VBUS) > V(UVLO), V(VBUS) > V(BAT), converter switching, V(BAT) = 3.2 V, ISYS = 0 A 4 mA
V(VBUS) > V(UVLO), V(VBUS) > V(BAT), converter switching, charge disable, V(BAT) = 3.8 V, ISYS = 100 µA 3.5 mA
I(BOOST) Battery discharge current in boost mode V(BAT) = 4.2 V, Boost mode, I(VBUS) = 0 A, converter switching 3.5 mA
VBUS/BAT POWER UP
V(VBUS_OP) VBUS operating voltage 3.9 6.2 V
V(VBUS_UVLOZ) VBUS for active I2C, no battery V(VBUS) rising 3.6 V
V(SLEEP) Sleep mode falling threshold V(VBUS) falling, V(VBUS-VBAT) 35 80 120 mV
V(SLEEPZ) Sleep mode rising threshold V(VBUS) rising, V(VBUS-VBAT) 170 250 350 mV
V(ACOV) VBUS over-voltage rising threshold V(VBUS) rising 6.2 6.6 V
V(ACOV_HYST) VBUS over-voltage falling hysteresis V(VBUS) falling 250 mV
V(BAT_UVLOZ) Battery for active I2C, no VBUS V(BAT) rising 2.3 V
V(BAT_DPL) Battery depletion threshold V(BAT) falling 2.4 2.6 V
V(BAT_DPL_HY) Battery depletion rising hysteresis V(BAT) rising 200 mV
V(VBUSMIN) Bad adapter detection threshold V(VBUS) falling 3.8 V
I(BADSRC) Bad adapter detection current source 30 mA
POWER PATH MANAGEMENT
V(SYS_MAX) Maximum DC system voltage output BATFET (Q4) off, V(BAT) up to 4.35 V 4.43 V
V(SYS_MIN) Minimum DC system voltage output REG01[3:1] = 101, V(SYS_MIN) = 3.5 V 3.5 3.65 V
RON(RBFET) Top reverse blocking MOSFET on-resistance between VBUS and PMIID 35 48 mΩ
RON(HSFET) Internal top switching MOSFET on-resistance between PMID and SW TJ = –40°C – 85°C 45 57 mΩ
TJ = -40°C – 125°C 45 65
RON(LSFET) Internal bottom switching MOSFET on-resistance between SW and PGND TJ = –40°C – 85°C 67 88 mΩ
TJ = -40°C – 125°C 67 98
V(FWD) BATFET forward voltage in supplement mode BAT discharge current 10 mA 30 mV
V(SYS_BAT) SYS/BAT comparator V(BAT) < V(SYS_MIN) , V(SYS) falling 80 mV
V(BAT) > V(SYS_MIN) , V(SYS) falling 180 mV
V(BATGD) Battery good comparator rising threshold V(BAT) rising 3.55 V
V(BATGD_HYST) Battery good comparator falling threshold V(BAT) falling 100 mV
BATTERY CHARGER
V(BAT_REG_ACC) Charge voltage regulation accuracy V(BAT) = 4.112 V and 4.208 V –0.5% 0.5%
I(ICHG_REG_ACC) Fast charge current regulation accuracy V(BAT) = 3.8 V, I(CHG) = 1024 mA, TJ = 25°C -4% 4%
V(BAT) = 3.8 V, I(CHG) = 1024 mA, TJ = -20°C – 125°C -7% 7%
V(BAT) = 3.8 V, ICHG = 1792 mA, TJ = -20°C – 125°C –10% 10%
I(CHG) Charge current with 20% option on V(BAT) = 3.1 V, I(CHG) = 104 mA, REG02 = 03 and
REG02[0] = 1		 75 175 mA
V(BATLOWV) Battery LOWV falling threshold Fast charge to precharge, REG04[1] = 1 2.6 2.8 2.9 V
V(BATLOWV_HYST) Battery LOWV rising threshold Precharge to fast charge, REG04[1] = 1
(Typical 200-mV hysteresis)		 2.8 3 3.1 V
I(PRECHG_ACC) Precharge current regulation accuracy V(BAT) = 2.6 V, I(CHG) = 256 mA –20% 20%
I(TYP_TERM_ACC) Typical termination current I(TERM) = 256 mA, I(CHG) = 2048 mA 265 mA
I(TERM_ACC) Termination current accuracy I(TERM) = 256 mA, I(CHG) = 2048 mA –22.5% 22.5%
V(SHORT) Battery short voltage V(BAT) falling 2.0 V
V(SHORT_HYST) Battery Short Voltage hysteresis V(BAT) rising 200 mV
I(SHORT) Battery short current V(BAT) < 2.2 V 100 mA
V(RECHG) Recharge threshold below VBAT_REG V(BAT) falling, REG04[0] = 0 100 mV
t(RECHG) Recharge deglitch time V(BAT) falling, REG04[0] = 0 20 ms
RON(BATFET) SYS-BAT MOSFET on-resistance TJ = 25°C 24 28 mΩ
TJ = –40°C – 125°C 24 35
INPUT VOLTAGE/CURRENT REGULATION
V(INDPM_REG_ACC) Input voltage regulation accuracy -2% 2%
I(USB_DPM) USB Input current regulation limit, V(BUS) = 5 V, current pulled from SW USB100 85 100 mA
USB150 125 150 mA
USB500 440 500 mA
USB900 750 900 mA
I(ADPT_DPM) Input current regulation accuracy I(ADP) = 1.5 A, REG00[2:0] = 101 1.3 1.5 A
IIN(START) Input current limit during system start up V(SYS) < 2.2 V 100 mA
KILIM IIN = KILIM/RILIM IIN(DPM) = 1.5 A 395 435 475 A x Ω
BAT OVERVOLTAGE PROTECTION
V(BATOVP) Battery overvoltage threshold V(BAT) rising, as percentage of V(BAT_REG) 104%
V(BATOVP_HYST) Battery overvoltage hysteresis V(BAT) falling, as percentage of V(BAT_REG) 2%
tBATOVP Battery overvoltage deglitch time to disable charge 1 µs
THERMAL REGULATION AND THERMAL SHUTDOWN
TJ Junction temperature regulation accuracy REG06[1:0] = 11 120 °C
T(SHUT) Thermal shutdown rising temperature Temperature increasing 160 °C
T(SHUT_HYS) Thermal shutdown hysteresis 30 °C
Thermal shutdown rising deglitch Temperature increasing delay 1 ms
Thermal shutdown falling deglitch Temperature decreasing delay 1 ms
COLD/HOT THERMISTER COMPARATOR
V(LTF) Cold temperature threshold, TS pin voltage rising threshold Charger suspends charge. as percentage to V(REGN) 73% 73.5% 74%
V(LTF_HYS) Cold temperature hysteresis, TS pin voltage falling As percentage to V(REGN) 0.4%
V(HTF) Hot temperature TS pin voltage rising threshold As percentage to V(REGN) 46.6% 47.2% 48.8%
V(TCO) Cut-off temperature TS pin voltage falling threshold As percentage to V(REGN) 44.2% 44.7% 45.2%
Deglitch time for temperature out of range detection V(TS) > V(LTF), or V(TS) < V(TCO), or V(TS) < V(HTF) 10 ms
V(BCOLD0) Cold temperature threshold, TS pin voltage rising threshold As percentage to V(REGN) REG02[1] = 0
(Approx. -10°C w/ 103AT) 		75.5% 76% 76.5%
V(BCOLD0_HYS) As percentage to V(REGN) REG02[1] = 0
(Approx. 1°C w/ 103AT)		 1%
V(BCOLD1) Cold temperature threshold 1, TS pin voltage rising threshold As percentage to V(REGN) REG02[1] = 1
(Approx. -20°C w/ 103AT) 		78.5% 79% 79.5%
V(BCOLD1_HYS) As percentage to V(REGN) REG02[1] = 1
(Approx. 1°C w/ 103AT)		 1%
V(BHOT0) Hot temperature threshold, TS pin voltage falling threshold As percentage to V(REGN) REG06[3:2] = 01
(Approx. 55°C w/ 103AT) 		35.5% 36% 36.5%
V(BHOT0_HYS) As percentage to V(REGN) REG06[3:2] = 01
(Approx. 3°C w/ 103AT)		 3%
V(BHOT1) Hot temperature threshold 1, TS pin voltage falling threshold As percentage to V(REGN) REG06[3:2] = 00
(Approx. 60°C w/ 103AT) 		32.5% 33% 33.5%
V(BHOT1_HYS) As percentage to V(REGN) REG06[3:2] = 00
(Approx. 3°C w/ 103AT)		 3%
V(BHOT2) Hot temperature threshold 2, TS pin voltage falling threshold As percentage to V(REGN) REG06[3:2] = 10
(Approx. 65°C w/ 103AT) 		29.5% 30% 30.5%
V(BHOT2_HYS) As percentage to V(REGN) REG06[3:2] = 10
(Approx. 3°C w/ 103AT)		 3%
CHARGE OVERCURRENT COMPARATOR
I(HSFET_OCP) HSFET cycle by cycle over-current threshold 4 7.5 A
V(LSFET_UCP) LSFET charge under-current falling threshold From sync mode to non-sync mode 100 mA
FSW PWM Switching frequency, and digital clock 1300 1500 1700 kHz
D(MAX) Maximum PWM duty cycle 97%
V(BTST_REFRESH) Bootstrap refresh comparator threshold V(BTST) - V(SW) when LSFET refresh pulse is requested, V(BUS) = 5 V 3.6 V
BOOST MODE OPERATION
V(OTG_REG_ACC) OTG output voltage I(VBUS) = 0, REG06[7:4] = 0111 (4.998 V) 5 V
OTG output voltage accuracy I(VBUS) = 0, REG06[7:4] = 0111 (4.998 V) -3% 3%
V(OTG_BAT) Battery voltage exiting OTG mode BAT falling, REG04[1] = 1 2.9 V
I(OTG) OTG mode output current REG01[0] = 0 1 A
REG01[0] = 1 1.5 A
V(OTG_OVP) OTG over-voltage threshold Rising threshold 5.8 6 V
V(OTG_OVP_HYS) OTG over-voltage threshold hysteresis Falling threshold 300 mV
I(OTG_LSOCP) LSFET cycle by cycle current limit 5 A
I(OTG_HSZCP) HSFET under current falling threshold 100 mA
I(RBFET_OCP) RBFET overcurrent threshold REG01[0] = 0 1.00 1.15 1.30 A
REG01[0] = 1 1.50 1.70 1.90
REGN LDO
V(REGN) REGN LDO output voltage V(VBUS) = 6 V, I(REGN) = 40 mA 4.8 5 5.5 V
V(VBUS) = 5 V, I(REGN) = 20 mA 4.7 4.8 V
I(REGN) REGN LDO current limit V(VBUS) = 5 V, V(REGN) = 3.8 V 50 mA
LOGIC I/O PIN CHARACTERISTICS (OTG, CE, STAT, QON, PSEL, PG)
VI(LO) Input low threshold 0.4 V
VIH Input high threshold (CE, STAT, QON, PSEL, PG) 1.3 V
VIH(OTG) Input high threshold (OTG) 1.1 V
VOUT(LO) Output low saturation voltage Sink current = 5 mA 0.4 V
I(BIAS) High level leakage current (OTG, CE, STAT , PSEL, PG) Pull-up rail 1.8 V 1 µA
I(BIAS) High level leakage current (QON) Pull-up rail 3.6 V 8 µA
I2C INTERFACE (SDA, SCL, INT)
VIH Input high threshold level VPULL-UP = 1.8 V, SDA and SCL 1.3 V
VIL Input low threshold level VPULL-UP = 1.8 V, SDA and SCL 0.4 V
VOL Output low threshold level Sink current = 5 mA 0.4 V
I(BIAS) High-level leakage current VPULL-UP = 1.8 V, SDA and SCL 1 µA
f(SCL) SCL clock frequency 400 kHz
DIGITAL CLOCK AND WATCHDOG TIMER
f(HIZ) Digital crude clock REGN LDO disabled 15 35 50 kHz
f(DIG) Digital clock REGN LDO enabled 1300 1500 1700 kHz

7.6 Timing Requirements

MIN TYP MAX UNIT
VBUS/BAT POWER UP
tBADSRC Bad source detection duration 30 ms
BOOST MODE OPERATION
tOTG_OCP_OFF OTG mode over-current protection off cycle time 32 ms
tOTG_OCP_ON OTG mode over-current protection on cycle time 260 µs
QON TIMING
tQON QON pin high time to turn on BATFET 2 ms
DIGITAL CLOCK AND WATCHDOG TIMER
tWDT REG05[5:4] = 11 REGN LDO disabled 112 160 s
REGN LDO enabled 136 160
bq24259 timing_slusbp6.gif Figure 1. I2C-Compatible Interface Timing Diagram

7.7 Typical Characteristics

Table 1. Table of Figures

FIGURE
Charging Efficiency vs Charging Current (DCR = 10 mΩ) Figure 2
System Efficiency vs System Load Current (DCR = 10 mΩ) Figure 3
Boost Mode Efficiency vs V(BUS) Load Current (DCR = 10 mΩ) Figure 4
SYS Voltage Regulation vs System Load Current Figure 5
Boost Mode VBUS Voltage Regulation (Typical Output = 4.998 V, REG06[7:4] = 0111) vs VBUS Load Current Figure 6
SYS Voltage vs Temperature Figure 7
BAT Voltage vs Temperature Figure 8
Input Current Limit vs Temperature Figure 9
Charge Current vs Package Temperature Figure 10
bq24259 D001_SLUSCF0.gif
VBUS = 5 V
Figure 2. Charge Efficiency vs Charge Current
bq24259 C003_SLUSBC1.png
Figure 4. Boost Mode Efficiency
vs VBUS Load Current
bq24259 C005_SLUSBC1.png
Typical Output = 4.998 V, REG06[7:4] = 0111
Figure 6. Boost Mode VBUS Voltage Regulation
vs VBUS Load Current
bq24259 C008_SLUSBC1.png
Figure 8. BAT Voltage vs Temperature
bq24259 C010_SLUSBC1.png
Figure 10. Charge Current vs Package Temperature
bq24259 D002_SLUSCF0.gif
VBUS = 5 V
Figure 3. System Efficiency
vs System Load Current
bq24259 C004_SLUSBC1.png
Figure 5. SYS Voltage Regulation
vs System Load Current
bq24259 C007_SLUSBC1.png
Figure 7. SYS Voltage vs Temperature
bq24259 C009_SLUSBC1.png
Figure 9. Input Current Limit vs Temperature