ZHCSF64B June 2016 – January 2018 ADS8910B , ADS8912B , ADS8914B
PRODUCTION DATA.
This register configures the contents of the 22-bit output data word (D[21:0]).
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | FPAR_LOC[1:0] | PAR_EN | DATA_VAL | |
R-0b | R-0b | R-0b | R-0b | R/W-00b | R/W-0b | R/W-0b |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | 0 | R | 0000b | Reserved bits. Reads return 0000b. |
3-2 | FPAR_LOC[1:0] | R/W | 00b | These bits control the data span for calculating the FTPAR bit (bit D[2] in the output data word). 00b = D[2] reflects even parity calculated for 4 MSB 01b = D[2] reflects even parity calculated for 8 MSB 10b = D[2] reflects even parity calculated for 12 MSB 11b = D[2] reflects even parity calculated for 16 MSB |
1 | PAR_EN | R/W | 0b | 0b = Output data does not contain any parity information D[3] = 0 D[2] = 0 1b = Parity information is appended to the LSB of the output data D[3] = Even parity calculated on bits D[21:4] D[2] = Even parity computed on selected number of MSB of D[21:4] as per FPAR_LOC[1:0] setting See Figure 42 for further details of parity computation. |
0 | DATA_VAL | R/W | 0b | These bits control bits D[21:4] of the output data word. 0b = 18-bit conversion output 1b = 18-bit contents of the fixed-pattern registers See PATN CNTL for more details. |