ZHCSKR7A February   2020  – February 2020 ADS8355

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      典型方框图
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1      Absolute Maximum Ratings
    2. 6.2      ESD Ratings
    3. 6.3      Recommended Operating Conditions
    4. 6.4      Thermal Information
    5. 6.5      Electrical Characteristics
    6. Table 1. Timing Requirements
    7. Table 2. Switching Characteristics
    8. 6.6      Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Reference
      2. 7.3.2 Analog Inputs
        1. 7.3.2.1 Analog Input: Full-Scale Range Selection
        2. 7.3.2.2 Analog Input: Single-Ended and Pseudo-Differential Configurations
      3. 7.3.3 Transfer Function
    4. 7.4 Device Functional Modes
      1. 7.4.1 Conversion Data Read: Dual-SDO Mode (Default)
      2. 7.4.2 Conversion Data Read: Single-SDO Mode
      3. 7.4.3 Low-Power Modes
        1. 7.4.3.1 STANDBY Mode
        2. 7.4.3.2 PD (Power-Down) Mode
    5. 7.5 Programming
      1. 7.5.1 Register Read/Write Operation
    6. 7.6 Register Map
      1. 7.6.1 ADS8355 Registers
        1. 7.6.1.1  PD_STANDBY Register (Offset = 4h) [reset = 0h]
          1. Table 9. PD_STANDBY Register Field Descriptions
        2. 7.6.1.2  PD_KEY Register (Offset = 5h) [reset = 0h]
          1. Table 10. PD_KEY Register Field Descriptions
        3. 7.6.1.3  SDO_CTRL Register (Offset = Dh) [reset = 0h]
          1. Table 11. SDO_CTRL Register Field Descriptions
        4. 7.6.1.4  DATA_OUT_CTRL Register (Offset = 11h) [reset = 0h]
          1. Table 12. DATA_OUT_CTRL Register Field Descriptions
        5. 7.6.1.5  REF_SEL Register (Offset = 20h) [reset = 0h]
          1. Table 13. REF_SEL Register Field Descriptions
        6. 7.6.1.6  REFDAC_A_LSB Register (Offset = 24h) [reset = 0h]
          1. Table 14. REFDAC_A_LSB Register Field Descriptions
        7. 7.6.1.7  REFDAC_A_MSB Register (Offset = 25h) [reset = 0h]
          1. Table 15. REFDAC_A_MSB Register Field Descriptions
        8. 7.6.1.8  REFDAC_B_LSB Register (Offset = 26h) [reset = 0h]
          1. Table 16. REFDAC_B_LSB Register Field Descriptions
        9. 7.6.1.9  REFDAC_B_MSB Register (Offset = 27h) [reset = 0h]
          1. Table 17. REFDAC_B_MSB Register Field Descriptions
        10. 7.6.1.10 INPUT_CONFIG Register (Offset = 28h) [reset = 0h]
          1. Table 18. INPUT_CONFIG Register Field Descriptions
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Input Amplifier Selection
      2. 8.1.2 Charge Kickback Filter
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 开发支持
    2. 11.2 文档支持
      1. 11.2.1 相关文档
    3. 11.3 接收文档更新通知
    4. 11.4 社区资源
    5. 11.5 商标
    6. 11.6 静电放电警告
    7. 11.7 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.5.1 Register Read/Write Operation

This device features configuration registers and supports the commands listed in Table 6 to access the internal configuration registers.

Table 6. Supported Commands

B[19:16] B[15:8] B[7:0] COMMAND ACRONYM COMMAND DESCRIPTION
0000 00000000000 00000000 NOP No operation. Next frame provides the ADC conversion result output on the SDO_X lines.
0001 <8-bit address> <8-bit data> WR_REG Write <8-bit data> to the <8-bit address>
0010 <8-bit address> 00000000 RD_REG Read contents from the <8-bit address>
0011 <8-bit address> <8-bit unmasked bits> SET_BITS Set <8-bit unmasked bits> from <8-bit address>
0100 <8-bit address> <8-bit unmasked bits> CLR_BITS Clear <8-bit unmasked bits> from <8-bit address>
Remaining combinations xxxxxxxxx xxxxxxxx Reserved These commands are reserved and treated by the device as no operation.

The ADS8355 supports two types of data transfer operations: data write (the host controller configures the device), and data read (the host controller reads data from the device).

Any data write to the device is always synchronous to the external clock provided on the SCLK pin. The WR_REG command writes the 8-bit data into the 8-bit address specified in the command string. The CLR_BITS command clears the specified bits (identified by 1) at the 8-bit address (without affecting the other bits), and the SET_BITS command sets the specified bits (identified by 1) at the 8-bit address (without affecting the other bits).

Figure 31 shows the digital waveform for a register read operation. A register read operation consists of two frames: one frame to initiate a register read and a second frame to read data from the register address provided in the first frame. As shown in Figure 31, the 8-bit register address and the 8-bit dummy data are sent over the SDI pin during the first 20-bit frame with the read command (0010b). The 20-bit command information is right-aligned with the frame. If a command frame is smaller than 20 bits, the contents of the command are discarded. If a frame has more than 20 bits, the last 20 bits are used to decode the operation. When CS goes from low to high, this read command is decoded and the requested register data are available for reading during the next frame. During the second frame, the first eight bits on SDO_A correspond to the requested register read. During the second frame, SDI can be used to initiate another operation or can be set to 0.

ADS8355 Reg_Read_BAS761.gifFigure 31. Register Read Operation

Figure 32 shows that for writing data to the register, one 20-bit frame is required. The frame contents are right-aligned. If a command frame is smaller than 20 bits, the contents of the command are discarded. If a frame has more than 20 bits, the last 20 bits are used to decode the operation. The 20-bit data on SDI consists of a 4-bit write command (0001b), set bit command (0011b), or clear bit command (0100b), an 8-bit register address, and 8-bit data. The write command is decoded on the CS rising edge and the specified register is updated with the 8-bit data specified during the register write operation.

ADS8355 Reg_Write_BAS761.gifFigure 32. Register Write Operation