ZHCSJ89B
January 2019 – July 2022
ADS8353-Q1
PRODUCTION DATA
1
特性
2
应用
3
说明
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Thermal Information
6.4
Recommended Operating Conditions
6.5
Electrical Characteristics
6.6
Timing Requirements
6.7
Switching Characteristics
6.8
Timing Diagram
6.9
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Reference
7.3.2
Analog Inputs
7.3.2.1
Analog Input: Full-Scale Range Selection
7.3.2.2
Analog Input: Single-Ended and Pseudo-Differential Configurations
7.3.3
Transfer Function
7.4
Device Functional Modes
7.5
Programming
7.5.1
Serial Interface
7.5.2
Write to User-Programmable Registers
7.5.3
Data Read Operation
7.5.3.1
Reading User-Programmable Registers
7.5.3.2
Conversion Data Read
7.5.3.2.1
32-CLK, Dual-SDO Mode (CFR.B11 = 0, CFR.B10 = 0, Default)
7.5.3.2.2
32-CLK, Single-SDO Mode (CFR.B11 = 0, CFR.B10 = 1)
7.5.4
Low-Power Modes
7.5.4.1
STANDBY Mode
7.5.4.2
Software Power-Down (SPD) Mode
7.5.5
Frame Abort, Reconversion, or Short-Cycling
7.6
Register Maps
7.6.1
ADS8353-Q1 Registers
8
Application and Implementation
8.1
Application Information
8.1.1
Input Amplifier Selection
8.1.2
Charge Kickback Filter
8.2
Typical Application
8.2.1
Design Requirements
8.2.2
Detailed Design Procedure
8.2.3
Application Curve
8.3
Power Supply Recommendations
8.4
Layout
8.4.1
Layout Guidelines
8.4.2
Layout Example
9
Device and Documentation Support
9.1
Device Support
9.1.1
Development Support
9.2
Documentation Support
9.2.1
Related Documentation
9.3
接收文档更新通知
9.4
支持资源
9.5
Trademarks
9.6
Electrostatic Discharge Caution
9.7
术语表
Mechanical, Packaging, and Orderable Information
封装选项
机械数据 (封装 | 引脚)
PW|16
MPDS361A
散热焊盘机械数据 (封装 | 引脚)
订购信息
zhcsj89b_oa
zhcsj89b_pm
8.4
Layout