SLAS611C October   2009  – January 2016 ADS5400

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Interleaving Adjustments
    7. 6.7 Timing Requirements
    8. 6.8 Switching Characteristics
    9. 6.9 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Input Configuration
      2. 7.3.2  Voltage Reference
      3. 7.3.3  Analog Input Over-Range Recovery Error
      4. 7.3.4  Clock Inputs
      5. 7.3.5  Over Range
      6. 7.3.6  Data Scramble
      7. 7.3.7  Test Patterns
      8. 7.3.8  Die Identification and Revision
      9. 7.3.9  Die Temperature Sensor
      10. 7.3.10 Interleaving
        1. 7.3.10.1 Gain Adjustment
        2. 7.3.10.2 Offset Adjustment
        3. 7.3.10.3 Input Clock Coarse Phase Adjustment
        4. 7.3.10.4 Input Clock Fine Phase Adjustment
    4. 7.4 Device Functional Modes
      1. 7.4.1 Output Bus and Clock Options
      2. 7.4.2 Reset and Synchronization
      3. 7.4.3 LVDS
    5. 7.5 Programming
      1. 7.5.1 Serial Interface
    6. 7.6 Register Maps
      1. 7.6.1 Serial Register Map
      2. 7.6.2 Description of Serial Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Clocking Source for ADS5400
        2. 8.2.2.2 Amplifier Selection
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 PowerPAD™ Package
      1. 10.3.1 Assembly Process
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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4 Revision History

Changes from B Revision (March 2010) to C Revision

  • Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section Go
  • Deleted Thermal Characteristics tableGo

Changes from A Revision (November 2009) to B Revision

  • Changed INL - Integral non- linearity error Max value From: 4 To: 4.5Go
  • Changed Worst harmonic/spur (other than HD2 and HD3), fIN = 1200 MHz TYP value From: 70 To 66Go
  • Changed Worst harmonic/spur (other than HD2 and HD3), fIN = 1700 MHz TYP value From: 66 To 64Go
  • Changed Total Harmonic Distortion, fIN = 125 MHz TYP value From: 73.5 To 71.7Go
  • Changed Total Harmonic Distortion, fIN = 600 MHz TYP value From: 68.5 To 67Go
  • Changed Total Harmonic Distortion, fIN = 850 MHz TYP value From: 68.5 To 66.5Go
  • Changed Total Harmonic Distortion, fIN = 1700 MHz TYP value From: 56.2 To 55.7Go
  • Changed Signal-to-noise and distortion, fIN = 125 MHz TYP value From: 58 To 58.5Go
  • Changed Signal-to-noise and distortion, fIN = 600 MHz TYP value From: 57.4 To 58.2Go
  • Changed Signal-to-noise and distortion, fIN = 850 MHz TYP value From: 57.3 To 57.8Go
  • Changed Signal-to-noise and distortion, fIN = 1200 MHz TYP value From: 57.2 To 57.5Go
  • Changed Signal-to-noise and distortion, fIN = 1700 MHz TYP value From: 54 To 54.2Go
  • Changed Effective number of bits (using SINAD in dBFS), fIN = 125 MHz TYP value From: 9.34 To 9.42Go
  • Changed Effective number of bits (using SINAD in dBFS), fIN = 600 MHz TYP value From: 9.24 To 9.37Go
  • Changed Effective number of bits (using SINAD in dBFS), fIN = 850 MHz TYP value From: 9.23 To 9.3Go
  • Changed INPUT CLOCK COARSE PHASE ADJUSTMENT, Integral Non-Linearity error Max value From: 4 To 5Go
  • Changed Table 5, BIT 4 From: 1 To: 0Go
  • Deleted note: (was not available on early samples) from SPI Register Reset in Table 5Go

Changes from * Revision (October 2009) to A Revision

  • Changed the FEATURES listGo
  • Deleted text "Internal pull-down resistor" from the SCLK, SDIO, and SDO pins in the Pin Functions tableGo
  • Changed the SDENB pin text From: "Internal pull-up resistor" To: "Internal 100kΩ pull-up resisto" in the Pin Functions tableGo
  • Added Note to the Pin Functions table - This pin contains an internal ~40kΩ pull-down resistor, to ground.Go
  • Changed Abs Max, Recommended Op Conditions, and Electrical Specs values. Go
  • Changed the description of the ANALOG INPUT entry in the Rec Op Condition table From: Differential input range To: Full-scale differential input rangeGo
  • Changed the Rec Op table, VCM - TYP value From: 2.5V To AVDD5/2Go
  • Changed the description of the ANALOG INPUT entry in the Elect Char table From: Differential input range To: Full-scale differential input rangeGo
  • Changed the Elect Char table, VCM - TYP value From: 2.5V To AVDD5/2Go
  • Changed the Timing Diagrams illustrationsGo
  • Changed Figure 1Go
  • Changed Figure 2Go
  • Changed Figure 3Go
  • Changed Figure 4Go
  • Changed Figure 5Go
  • Changed the TYPICAL CHARACTERISTICS, Conditions Note From: DVDD3 = 3.3 V, and 3.3-VPP differential clock To: DVDD = 3.3V and 1.5 VPP differential clockGo
  • Added subsection - Analog Input Over-Range Recovery ErrorGo
  • Changed the Clock Inputs subsectionGo
  • Changed the Test Patterns subsectionGo
  • Changed the Interleaving subsectionGo
  • Changed Table 6 BIT <7:3>, Title and descriptionGo
  • Changed Table 7 BIT <0>, Default setting description, and BIT <7:2> descriptionGo
  • Changed Table 8 BIT <0>, Default setting descriptionGo
  • Changed Serial Register 0x06 (Read or Write) (Table 10). Bits 4 and 5 From TBD To: 0Go
  • Deleted Table 10 description comment from BIT <7:6> 11: (this mode is not working properly on early samples - will be fixed)Go
  • Changed the Power Supplies subsectionGo
  • Added Figure 40 - Was TBDGo