SLAS669E September   2010  – may 2020 ADS5400-SP

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Block Diagram
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Timing Characteristics
    8. 6.8 Interleaving Adjustments
    9. 6.9 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Input Configuration
      2. 7.3.2  Voltage Reference
      3. 7.3.3  Analog Input Over-Range Recovery Error
      4. 7.3.4  Clock Inputs
      5. 7.3.5  Over Range
      6. 7.3.6  Data Scramble
      7. 7.3.7  Test Patterns
      8. 7.3.8  Die Identification and Revision
      9. 7.3.9  Die Temperature Sensor
      10. 7.3.10 Interleaving
        1. 7.3.10.1 Gain Adjustment
        2. 7.3.10.2 Offset Adjustment
        3. 7.3.10.3 Input Clock Coarse Phase Adjustment
        4. 7.3.10.4 Input Clock Fine Phase Adjustment
    4. 7.4 Device Functional Modes
      1. 7.4.1 Output Bus and Clock Options
      2. 7.4.2 Reset and Synchronization
      3. 7.4.3 LVDS
    5. 7.5 Programming
      1. 7.5.1 Serial Interface
        1. Table 2. Instruction Byte of the Serial Interface
    6. 7.6 Serial Register Map
      1. 7.6.1 Description of Serial Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Clocking Source for ADS5400-SP
        2. 8.2.2.2 Amplifier Selection
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
        1. 11.1.1.1 Definition of Specifications
    2. 11.2 Documentation Support
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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7.6.1 Description of Serial Registers

Each register function is explained in detail below.

Table 5. Serial Register 0x00 (Read or Write)

Address (hex) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
0x00 Analog Gain Adjustment bits<11:4>
Defaults 0 0 0 0 0 0 0 0
BIT <7:0> Analog gain adjustment (most significant 8 bits of a 12 bit word)
All 12-bits in this adjustment in address 0x00 and 0x01 set to 0000 0000 0000 = fullscale analog input 2.0VPP
All 12-bits in this adjustment in address 0x00 and 0x01 set to 1111 1111 1111 = fullscale analog input 1.52VPP
Step adjustment resolution is 120µV.
Can be used for one-time setting or continual calibration of analog signal path gain.

Table 6. Serial Register 0x01 (Read or Write)

Address (hex) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
0x01 Analog Gain Adjustment bits<3:0> 3 or 4-pin SPI SPI Reset 0 0
Defaults 0 0 0 0 0 0 0 0
BIT <0:1> RESERVED
0 set to 0 if writing this register
1 do not set to 1
BIT <2> SPI Register Reset
0 altered register settings are kept
1 resets all SPI registers to defaults (self clearing)
BIT <3> Set SPI mode to 3- or 4-pin
0 3-pin SPI (read/write on SDIO, SDO not used)
1 4-pin SPI (SDIO is write, SDO is read)
BIT <7:4> Analog gain adjustment continued (least significant 4 bits of a 12-bit word)
All 12-bits in this adjustment in address 0x00 and 0x01 set to 0000 0000 0000 = fullscale analog input 2VPP
All 12-bits in this adjustment in address 0x00 and 0x01 set to 1111 1111 1111 = fullscale analog input 1.52VPP
Step adjustment resolution is 120µV.
Can be used for one-time setting or continual calibration of analog signal path gain.

Table 7. Serial Register 0x02 (Read or Write)

Address (hex) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
0x02 Coarse Clock Phase Adjustment bits<4:0> 0 Clock Divider Single or Dual Bus
Defaults 0 0 0 0 0 0 0 0
BIT <0> Single or Dual Bus Output Selection
0 dual bus output (A and B)
1 single bus output (A)
BIT <1> Output Clock Divider
0 CLKOUT equals CLKIN divide by 4 (not available in single bus mode)
1 CLKOUT equals CLKIN divide by 2
BIT <2> RESERVED
0 set to 0 if writing this register
1 do not set to 1
BIT <7:3> Input Clock Coarse Phase Adjustment
Use as a coarse adjustment of input clock phase. The 5-bit adjustment provides a step size of ~2.4ps across a range from code 00000 = 0 ps to code 11111 = 73ps.

Table 8. Serial Register 0x03 (Read or Write)

Address (hex) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
0x03 Fine Clock Phase Adjustment bits<5:0> 0 Analog Offset bit<8>
Defaults 0 0 0 0 0 0 0 factory set
BIT <0> Analog Offset control (most significant bit of 9-bit word)
All 9-bits in this adjustment in address 0x03 and 0x04 set to 0 0000 0000 = -30mV (TBD)
All 9-bits in this adjustment in address 0x03 and 0x04 set to 1 1111 1111 = +30mV (TBD)
Step adjustment resolution is 120µV (or 1/4 LSB). Adjustments can be used for calibration of analog signal path offset (for instance offset error induced outside of the ADC) or to match multiple ADC offsets.
The default setting for this register is factory set to provide ~0mV of ADC offset in the output codes and is unique for each device.
BIT <1> RESERVED
0 set to 0 if writing this register
1 do not set to 1
BIT <7:2> Fine Clock Phase Adjustment
Use as a fine adjustment of the input clock phase. The 6-bit adjustment provides a step resolution of ~116fs across a range from code 000000 = 0ps to code 111111 = 7.4ps. Can be used in conjuction with Coarse Clock Phase Adjustment in address 0x02.

Table 9. Serial Register 0x04 (Read or Write)

Address (hex) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
0x04 Analog Offset Control bits<7:0>
Defaults factory set
BIT <7:0> Analog Offset control continued (least significant bits of 9-bit word)
All 9-bits in this adjustment in address 0x03 and 0x04 set to 0 0000 0000 = -30mV (TBD)
All 9-bits in this adjustment in address 0x03 and 0x04 set to 1 1111 1111 = +30mV (TBD)
Step adjustment resolution is 120uV (or 1/4 LSB). Adjustments can be used for calibration of analog signal path offset (for instance offset error induced outside of the ADC) or to match multiple ADC offsets.
The default setting for this register is factory set to provide ~0mV of ADC offset in the output codes and is unique for each device.
Performance of the ADC is not specified across the entire offset control range. Some performance degradation is expected as larger offsets are programmed.

Table 10. Serial Register 0x05 (Read or Write)

Address (hex) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
0x05 Temp Sensor Powerdown reserved Sync Mode Data Format Reference Stagger Output 0
Defaults 0 0 1 0 0 0 0 0
BIT <0> RESERVED
0 set to 0 if writing this register
1 do not set to 1
BIT <1> Stagger Output Bus
0 Output bus A and B aligned
1 Output bus A and B staggered (see timing diagrams)
BIT <2> Enable External Reference
0 Enable internal reference
1 Enable external reference
BIT <3> Set Data Output Format
0 Enable offset binary
1 Enable two's complement
BIT <4> Set Sync Mode
0 Disable data synchronization mode
1 Enable data synchronization mode
When enabled, the OVR pin(s) are replaced with SYNC output signal(s). The SYNC output signal is time-aligned with the output data matching the corresponding input sample and RESET input pulse
BIT <5> RESERVED
0
1 set to 1 if writing this register
BIT <6> Powerdown
0 device active
1 device in low power mode (sleep mode)
BIT <7> Temperature Sensor
0 temperature sensor inactive
1 temperature sensor active, independent of powerdown bit in Bit<6>, allows reading of temp sensor while the rest of the ADC is in sleep mode

Table 11. Serial Register 0x06 (Read or Write)

Address (hex) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
0x06 Data output mode LVDS termination LVDS current Force LVDS outputs
Defaults 0 0 0 0 0 1 0 0
BIT <0:1> Force LVDS outputs
00 and 01 normal operating mode (LVDS is outputting sampled data bits)
10 forces the LVDS outputs to all logic zeros (data and clock out) - for level check
11 forces the LVDS outputs to all logic ones (data and clock out) - for level check
BIT <3:2> Set LVDS output current
00 2.5mA
01 3.5mA (default)
10 4.5mA
11 5.5mA
BIT <5:4> Set Internal LVDS termination differential resistor (for LVDS outputs only)
00 and 01 no internal termination
10 internal 200Ω resistor selected
11 internal 100Ω resistor selected
BIT <7:6> Control Data Output Mode
00 normal mode (LVDS is outputting sampled data bits)
01 scrambled output mode (D11:D1 is XOR'd with D0)
10 output data is replaced with PRBS test pattern (7-bit sequence)
11 output data is replaced with toggling test pattern (all 1s, then all 0s, then all 1s, etc.....on all bits)

Table 12. Serial Register 0x08 (Read only)

Address (hex) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
0x08 Die temperature bits<7:0>
Defaults depends on reading from temperature sensor
BIT <7:0> Die temperature readout
if enabled in register 0x05. To obtain the die temperature in Celsius, convert the 8-bit word to decimal and subtract 78.
<7:0> = 0x00 = 00000000, measured temperature is 0-78 = -78°C
<7:0> = 0x73 = 01110011, measured temperature is 115 - 78 = 37°C
<7:0> = 0xAF, measured temperature is 175 - 78 = 97°C

Table 13. Serial Register 0x09 (Read only)

Address (hex) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
0x09 000 0000 Memory error
Defaults 000 0000 0
BIT <7:1> RESERVED
set to 0 if writing this register
do not set to 1
BIT <0> Memory Error Indicator
Registers 0x00 through 0x07 have multiple redundancy. If any copy disagrees with the others, an error is flagged in this bit. This is for systems that require the highest level of assurance that the device remains programmed in the proper state and indication of an error if something changes unexpectedly.

Table 14. Serial Register 0x0A (Read only)

Address (hex) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
0x0A 0000 0000
Defaults 0000 0000
BIT <7:0> RESERVED
set to 0 if writing this register
do not set to 1

Table 15. Serial Register 0x17 through 0x1E (Read only)

Address (hex) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
0x17 - 0x1E Die ID
Defaults factory set
BIT <7:0> Die Identification Bits
Each of these eight registers contains 8-bits of a 64-bit unique die identifier.

Table 16. Serial Register 0x1F (Read only)

Address (hex) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
0x1F Die Revision Number
Defaults factory set
BIT <7:0> Die revision
Provides design revision information.