TXV0108
- Configurable design allows each port to operate with a power supply range from 1.14V to 3.6V
- Supports up to 500Mbps for 1.65V to 3.6V
- Meets RGMII 2.0 timing specifications:
- < 750ps rise and fall time
- < ± 5 % duty cycle distortion
- < ± 400 ps channel to channel skew
- Up to 250Mbps/Channel
-
Integrated 10 Ω damping output resistor to minimize signal reflections
-
High drive strength (up to 12mA at 3.6V)
- Fully configurable symmetric dual-rail design
- Optimal signal integrity performance with 390ps peak-to-peak jitter for 1.8V to 3.3V
- Features VCC isolation and VCC disconnect
- Ioff supports partial-power-down mode operation
- Latch-up performance exceeds 100mA per JESD 78, Class II
- ESD protection exceeds JESD 22:
- 2000V Human-Body Model
- 1000V Charged-Device Model
- Low power consumption:
- 10µA maximum (25°C)
- 20µA maximum (–40°C to 125°C)
- Operating temperature from –40°C to +125°C
- Pin compatible with SN74AVC8T245 (VQFN)
The TXV0108 is an 8-bit, dual-supply direction controlled low-skew, low-jitter voltage translation device. This device can be used for redriving, voltage translation, and power isolation when implementing skew sensitive interface, such as RGMII between Ethernet MAC and PHY devices. The Ax I/O pins and control pins (DIR, OE) are referenced to VCCA logic levels, and Bx I/O pins are referenced to VCCB logic levels. This device has improved channel-to-channel skew, duty cycle distortion and symmetric rise and fall time for applications requiring strict timing conditions.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, thus preventing damaging current backflow through the device when it is powered down.
The VCC isolation feature is designed so that if either VCC supply is at or near 0V both ports will switch to a high-impedance state. This feature enables power isolation for communications across multiple MACs and PHYs, and is beneficial in situations where MACs and PHYs are powered up asynchronously preventing current backflow between devices.
A High on DIR allows data transmission from A to B while a Low on DIR allows data transmission from B to A when OE is set to Low. When OE is set to High, both Ax and Bx pins will be forced into a high-impedance state. See Device Functional Modes for a summary of the operation of the control logic.
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | TXV0108 8-Bit Direction Controlled Low-Skew, Low-Jitter Voltage Translator or Buffer datasheet (Rev. A) | PDF | HTML | 2024/4/12 | ||
| Application brief | Enabling AI Accelerators with Voltage Level Translation and Analog Multiplexing (Rev. A) | PDF | HTML | 2025/9/29 | |||
| 應用說明 | Schematic Checklist - A Guide to Designing With Fixed or Direction Control Translators | PDF | HTML | 2024/10/2 | |||
| 應用說明 | Schematic Checklist - A Guide to Designing with Auto-Bidirectional Translators | PDF | HTML | 2024/7/12 | |||
| 應用說明 | Understanding Transient Drive Strength vs. DC Drive Strength in Level-Shifters (Rev. A) | PDF | HTML | 2024/7/3 | |||
| 應用說明 | Overcoming Design Challenges - Implementing High Performance Interfaces | PDF | HTML | 2023/12/12 | |||
| Application brief | Supporting Time and Skew Sensitive Interfaces with TI's TXV Level-Shifter | PDF | HTML | 2023/10/27 | |||
| Application brief | Enabling Industrial and Automotive Ethernet RGMII Interfaces with Voltage Transl | PDF | HTML | 2023/8/2 |
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14-24-NL-LOGIC-EVM — 適用於 14 針腳至 24 針腳無引線封裝的邏輯產品通用評估模組
14-24-NL-LOGIC-EVM 是一款靈活的評估模組 (EVM)，設計用於支援任何具有 14 針腳至 24 針腳 BQA、BQB、RGY、RSV、RJW 或 RHL 封裝的邏輯或轉換裝置。
TXV0108-EVM — TXV0108 評估模組
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| VQFN (RGY) | 24 | Ultra Librarian |