產品詳細資料

Bits (#) 4 Data rate (max) (Mbps) 24 Topology Open drain, Push-Pull Direction control (typ) Auto-direction Vin (min) (V) 1.65 Vin (max) (V) 3.6 Vout (min) (V) 2.3 Vout (max) (V) 5.5 Applications GPIO, I2C, JTAG, MDIO, SDIO, SMBus, SPI, UART Features Edge rate accelerator, Output enable Prop delay (ns) 124 Technology family TXS Supply current (max) (mA) 0.025 Rating Catalog Operating temperature range (°C) -40 to 125
Bits (#) 4 Data rate (max) (Mbps) 24 Topology Open drain, Push-Pull Direction control (typ) Auto-direction Vin (min) (V) 1.65 Vin (max) (V) 3.6 Vout (min) (V) 2.3 Vout (max) (V) 5.5 Applications GPIO, I2C, JTAG, MDIO, SDIO, SMBus, SPI, UART Features Edge rate accelerator, Output enable Prop delay (ns) 124 Technology family TXS Supply current (max) (mA) 0.025 Rating Catalog Operating temperature range (°C) -40 to 125
VQFN (RGY) 14 12.25 mm² (3.5 mm × 3.5 mm) SOIC (D) 14 51.9 mm² (8.65 mm × 6 mm) NFBGA (NMN) 12 5 mm² (2 mm × 2.5 mm) WQFN (BQA) 14 7.5 mm² (3 mm × 2.5 mm) UQFN (RUT) 12 3.4 mm² (2 mm × 1.7 mm) DSBGA (YZT) 12 3.9375 mm² (— mm × — mm) TSSOP (PW) 14 32 mm² (5 mm × 6.4 mm)
  • No direction-control signal needed
  • Maximum data rates:
    • 24Mbps (push pull)
    • 2Mbps (open drain)
  • Available in the Texas Instruments NanoFree™ package
  • 1.65 V to 3.6 V on A port and 2.3 V to 5.5 V on B port (V CCA ≤ V CCB)
  • No power-supply sequencing required – V CCA or V CCB can be ramped first
  • Latch-up performance exceeds 100 mA per JESD 78, class II
  • ESD protection exceeds JESD 22:
    • A port:
      • 2000-V Human-Body Model (A114-B)
      • 200-V Machine Model (A115-A)
      • 1000-V Charged-Device Model (C101)
    • B port:
      • 15-kV Human-Body Model (A114-B)
      • 200-V Machine Model (A115-A)
      • 1000-V Charged-Device Model (C101)
  • IEC 61000-4-2 ESD (B port):
    • ±8-kV contact discharge
    • ±10-kV air-gap discharge
  • No direction-control signal needed
  • Maximum data rates:
    • 24Mbps (push pull)
    • 2Mbps (open drain)
  • Available in the Texas Instruments NanoFree™ package
  • 1.65 V to 3.6 V on A port and 2.3 V to 5.5 V on B port (V CCA ≤ V CCB)
  • No power-supply sequencing required – V CCA or V CCB can be ramped first
  • Latch-up performance exceeds 100 mA per JESD 78, class II
  • ESD protection exceeds JESD 22:
    • A port:
      • 2000-V Human-Body Model (A114-B)
      • 200-V Machine Model (A115-A)
      • 1000-V Charged-Device Model (C101)
    • B port:
      • 15-kV Human-Body Model (A114-B)
      • 200-V Machine Model (A115-A)
      • 1000-V Charged-Device Model (C101)
  • IEC 61000-4-2 ESD (B port):
    • ±8-kV contact discharge
    • ±10-kV air-gap discharge

This 4-bit non-inverting translator uses two separate configurable power-supply rails. The A port is designed to track V CCA. V CCA accepts any supply voltage from 1.65 V to 3.6 V. V CCA must be less than or equal to V CCB. The B port is designed to track V CCB. V CCB accepts any supply voltage from 2.3 V to 5.5 V. This allows for low-voltage bidirectional translation between any of the 1.8-V, 2.5-V, 3.3-V, and 5-V voltage nodes.

When the output-enable (OE) input is low, all outputs are placed in the high-impedance state.

The TXS0104E is designed so that the OE input circuit is supplied by V CCA.

For the high-impedance state during power up or power down, tie OE to GND through a pull-down resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.

This 4-bit non-inverting translator uses two separate configurable power-supply rails. The A port is designed to track V CCA. V CCA accepts any supply voltage from 1.65 V to 3.6 V. V CCA must be less than or equal to V CCB. The B port is designed to track V CCB. V CCB accepts any supply voltage from 2.3 V to 5.5 V. This allows for low-voltage bidirectional translation between any of the 1.8-V, 2.5-V, 3.3-V, and 5-V voltage nodes.

When the output-enable (OE) input is low, all outputs are placed in the high-impedance state.

The TXS0104E is designed so that the OE input circuit is supplied by V CCA.

For the high-impedance state during power up or power down, tie OE to GND through a pull-down resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.

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CC256XMS432BTBLESW — MSP432 MCU 的 TI 雙模式藍牙架構

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lock = 需要匯出核准 (1 分鐘)
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模擬型號

TXS0104E IBIS Model (Rev. C)

SCEM560C.ZIP (64 KB) - IBIS 模型
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參考設計

TIDA-00403 — 使用 TLV320AIC3268 miniDSP 轉碼器的超音波距離量測參考設計

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封裝 針腳 CAD 符號、佔位空間與 3D 模型
VQFN (RGY) 14 Ultra Librarian
SOIC (D) 14 Ultra Librarian
NFBGA (NMN) 12 Ultra Librarian
WQFN (BQA) 14 Ultra Librarian
UQFN (RUT) 12 Ultra Librarian
DSBGA (YZT) 12 Ultra Librarian
TSSOP (PW) 14 Ultra Librarian

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