TPS7H4102-SEP
- Total ionizing dose (TID)
characterized
- Radiation hardness assurance (RHA) availability up to 100krad(Si)
- Single-event effects (SEE)
characterized
- Single-event latchup (SEL), single-event burnout (SEB), and single-event gate rupture (SEGR) immune up to linear energy transfer (LET) = 75MeV-cm2/mg*
- Single-event functional interrupt (SEFI) and single-event transient (SET) characterized up to LET = 75MeV-cm2/mg*
- Input voltage range from 3V to 7V
- Up to 3A of maximum output current per channel or more when channels are paralleled
- Typical efficiency of 91.1% (typ.) at VIN = 5V, VOUT = 1.8V, IOUT = 1A at fSW = 500kHz
- Integrated 62mΩ (HS) and 55mΩ (LS) MOSFETs (typ. at VIN = 5V)
- Flexible switching frequency:
- 100kHz to 1MHz, internal oscillator
- External synchronization capability
- Accurate voltage reference of 599.48mV ± 1% over line, temperature, and TID
- Monotonic start-up into pre-biased outputs
- Per channel (CHx)
- Adjustable slope compensation (RSCx)
- Adjustable soft-start (SS_TRx)
- Power-good output monitor for undervoltage and overvoltage (PWRGDx)
- Input enable (ENx)
- Sequence up and reverse sequence down when using EN_SEQ (only valid for TPS7H4104)
- Plastic packages outgas tested per ASTM E595
- Available in military (–55°C to 125°C) temp range
The TPS7H4104 and TPS7H4102 are 7V, 3A per channel, multichannel, peak-current mode, synchronous buck converters optimized for use in area sensitive, space environment applications. The device incorporates four (TPS7H4104) or two (TPS7H4102) identical channels that can be use to step down the power input voltage into independent voltages up to 3A per phase or interleaved to increment the output current up to 12A (TPS7H4104) or 6A (TPS7H4102).
Each channel incorporates the high-side and low-side power MOSFETs with programmable soft-start and slope compensation. Additionally, per channel power-good flags and enable signals are provided. The TPS7H4104 also includes an EN_SEQ input that enables a sequential power‑up and a reverse‑sequence power‑down.
Various current limit mechanisms are included for robust current limiting during fault conditions. Thermal shutdown disables the device when the die temperature exceeds thermal limit.
技術文件
設計與開發
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TPS7H4102EVM — TPS7H4102 評估模組
TPS7H410X-CALC — TPS7H4104/2 component calculator
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| HTQFP (PAP) | 64 | Ultra Librarian |
訂購與品質
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。