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DDR 記憶體電源 IC

TPS7H3301-SP

現行

Radiation-hardened, QML-V, 2.3V to 3.5V input, 3A sink and source DDR termination LDO regulator

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產品規格表

TPS7H3301-SP

現行
產品規格表 立即訂購

產品詳細資料

DDR memory type DDR2, DDR3, DDR4 Control mode S3, S4/S5 Iout VTT (max) (A) 3 Iq (typ) (mA) 18 Output VREF, VTT Vin (min) (V) 0.9 Vin (max) (V) 3.5 Features Complete Solution, Shutdown Pin for S3 Rating Space Operating temperature range (°C) -55 to 125 Regulator type Linear Regulator Vin bias (max) (V) 3.5 Vin bias (min) (V) 2.375 Vout VTT (min) (V) 0.6
DDR memory type DDR2, DDR3, DDR4 Control mode S3, S4/S5 Iout VTT (max) (A) 3 Iq (typ) (mA) 18 Output VREF, VTT Vin (min) (V) 0.9 Vin (max) (V) 3.5 Features Complete Solution, Shutdown Pin for S3 Rating Space Operating temperature range (°C) -55 to 125 Regulator type Linear Regulator Vin bias (max) (V) 3.5 Vin bias (min) (V) 2.375 Vout VTT (min) (V) 0.6
CFP (HKR) 16 105.6 mm² (— mm × — mm)
  • 5962R14228(1):
    • Radiation hardness assurance (RHA) qualified to total ionizing dose (TID) 100 krad(Si)
    • Single event latch-up (SEL), single event gate rupture (SEGR), single event burnout (SEB) immune to LET = 70 MeV-cm2/mg(2)
    • Single event transient (SET), single event functional interrupt (SEFI), and single event upset (SEU) characterized to 70 MeV-cm2/mg(2)
  • Supports DDR, DDR2, DDR3, DDR3L, and DDR4 termination applications
  • Input voltage: supports a 2.5-V and 3.3-V rail(3)
  • Separate low-voltage input (VLDOIN) down to 0.9 V for improved power efficiency(3)
  • 3-A sink and source termination regulator includes droop compensation
  • Enable input and power-good output for power supply sequencing
  • VTT termination regulator
    • Output voltage range: 0.5 to 1.75 V
    • 3-A sink and source current
  • Integrated precision voltage divider network with sense input
  • Remote sensing (VTTSNS)
  • VTTREF buffered reference

    • 49% to 51% accuracy with respect to VDDQSNS (±3 mA)

    • ±10-mA sink and source current
  • Undervoltage lockout (UVLO) and overcurrent limit (OCL) functionality integrated
  • 5962R14228(1):
    • Radiation hardness assurance (RHA) qualified to total ionizing dose (TID) 100 krad(Si)
    • Single event latch-up (SEL), single event gate rupture (SEGR), single event burnout (SEB) immune to LET = 70 MeV-cm2/mg(2)
    • Single event transient (SET), single event functional interrupt (SEFI), and single event upset (SEU) characterized to 70 MeV-cm2/mg(2)
  • Supports DDR, DDR2, DDR3, DDR3L, and DDR4 termination applications
  • Input voltage: supports a 2.5-V and 3.3-V rail(3)
  • Separate low-voltage input (VLDOIN) down to 0.9 V for improved power efficiency(3)
  • 3-A sink and source termination regulator includes droop compensation
  • Enable input and power-good output for power supply sequencing
  • VTT termination regulator
    • Output voltage range: 0.5 to 1.75 V
    • 3-A sink and source current
  • Integrated precision voltage divider network with sense input
  • Remote sensing (VTTSNS)
  • VTTREF buffered reference

    • 49% to 51% accuracy with respect to VDDQSNS (±3 mA)

    • ±10-mA sink and source current
  • Undervoltage lockout (UVLO) and overcurrent limit (OCL) functionality integrated

The TPS7H3301-SP is a TID and SEE radiation-hardened double data rate (DDR) 3-A termination regulator with built-in VTTREF buffer. The regulator is specifically designed to provide a complete, compact, low-noise solution for space DDR termination applications such as single board computers, solid state recorders, and payload processing.

The TPS7H3301-SP supports DDR VTT termination applications using DDR, DDR2, DDR3, DDR4. The fast transient response of the TPS7H3301-SP VTT regulator allows for a very stable supply during read/write conditions. During transients, the fast tracking feature of the VTTREF supply minimizes any voltage offset between VTT/Vo and VTTREF. To enable simple power sequencing, both an enable input and a power-good output (PGOOD) have been integrated into the TPS7H3301-SP. The PGOOD output is open-drain so it can be tied to multiple open-drain outputs to monitor when all supplies have come into regulation. The enable signal can also be used to discharge VTT/Vo during suspend to RAM (S3) power down mode.

The TPS7H3301-SP is a TID and SEE radiation-hardened double data rate (DDR) 3-A termination regulator with built-in VTTREF buffer. The regulator is specifically designed to provide a complete, compact, low-noise solution for space DDR termination applications such as single board computers, solid state recorders, and payload processing.

The TPS7H3301-SP supports DDR VTT termination applications using DDR, DDR2, DDR3, DDR4. The fast transient response of the TPS7H3301-SP VTT regulator allows for a very stable supply during read/write conditions. During transients, the fast tracking feature of the VTTREF supply minimizes any voltage offset between VTT/Vo and VTTREF. To enable simple power sequencing, both an enable input and a power-good output (PGOOD) have been integrated into the TPS7H3301-SP. The PGOOD output is open-drain so it can be tied to multiple open-drain outputs to monitor when all supplies have come into regulation. The enable signal can also be used to discharge VTT/Vo during suspend to RAM (S3) power down mode.
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技術文件

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重要文件 類型 標題 格式選項 下載最新的英文版本 日期
* 資料表 TPS7H3301-SP Sink and Source Radiation-Hardened 3-A DDR Termination Regulator With Built-In VTTREF Buffer datasheet (Rev. C) PDF | HTML 2024/9/27
* 輻射及可靠性報告 TPS7H3301-SP and TPS7H3302-SP Single-Event Effects Radiation Report (Rev. C) 2024/1/26
* 輻射及可靠性報告 TPS7H3301-SP Neutron Displacement Damage Characterization 2019/4/12
* 輻射及可靠性報告 TPS7H3301-SP Total Ionizing Dose Radiation Report 2016/7/1
* SMD TPS7H3301-SP SMD 5962-14228 2016/7/8
選擇指南 TI Space Products (Rev. L) 2026/3/27
應用說明 Hermetic Package Reflow Profiles, Termination Finishes, and Lead Trim and Form (Rev. A) PDF | HTML 2025/11/5
Application brief DLA Approved Optimizations for QML Products (Rev. C) PDF | HTML 2025/6/17
應用說明 Heavy Ion Orbital Environment Single-Event Effects Estimations (Rev. B) PDF | HTML 2025/6/10
更多文件說明 TI Engineering Evaluation Units vs. MIL-PRF-38535 QML Class V Processing (Rev. B) 2025/2/20
應用說明 Using Space Grade Power Components to Power AMD Kintex XQRKU060 FPGA PDF | HTML 2023/11/8
應用說明 Using Space Grade Power Components to Power Microchip RT PolarFire FPGA PDF | HTML 2023/9/20
應用說明 QML flow, its importance, and obtaining lot information (Rev. C) 2023/8/30
應用說明 Space Grade Power Solution for Microsemi RTG4 PDF | HTML 2023/5/2
應用說明 TI Space Rated Power Solution for Microsemi® RTG4™ FPGA (Rev. B) PDF | HTML 2023/1/19
應用說明 Single-Event Effects Confidence Interval Calculations (Rev. A) PDF | HTML 2022/10/19
應用說明 DLA Standard Microcircuit Drawings (SMD) and JAN Part Numbers Primer 2020/8/21
應用說明 DDR VTT Power Solutions: A Competitive Analysis (Rev. A) 2020/7/9
電子書 Radiation Handbook for Electronics (Rev. A) 2019/5/21
應用說明 External Soft-Start Circuit for TPS7H3301-SP Power-Up Sequencing Applications 2016/7/7
技術文章 7 things to know about spacecraft subsystems before your next trip to Mars PDF | HTML 2016/7/6

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開發板

TPS7H3301EVM-CVAL — TPS7H3301-SP DDR 終端評估模組

TPS7H3301-SP 源極/汲極雙資料速率 (DDR) 終端穩壓器是專為支援低雜訊應用的系統需求所設計。

這是一款整合式解決方案，具有縮小系統解決方案尺寸、提升效率以及簡化系統設計整合的特色。

使用指南: PDF
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開發套件

ALPHA-XILINX-KU060-SPACE — 附帶 TI 電源且適用於 Xilinx® Kintex® UltraScale™ XQRKU060 FPGA 的 Alpha Data® 主機板

This is a development kit for the Xilinx® XQRKU060 FPGA with industrial -1 speed grade. ADA-SDEV-KIT2 has a modular board design with a XRTC-compatible configuration module, two FMC connectors, DDR3 DRAM, system monitoring, and space-grade TI power management and temperature-sensing solutions.
從：Alpha Data Parallel Systems Ltd.
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模擬型號

TPS7H3301-SP PSpice Transient Model (Rev. B)

SLVMBF1B.ZIP (116 KB) - PSpice 模型
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模擬型號

TPS7H3301-SP Unencrypted PSPICE Transient Model

SLVMDD2.ZIP (196 KB) - PSpice 模型
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計算工具

SLVC650 — TPS7H3301-SP Calculator

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CFP (HKR) 16 Ultra Librarian
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