TPS65919-Q1
- Qualified for Automotive Applications
- AEC-Q100 Qualified With the Following Results:
- Device Temperature Grade 2: –40°C to +105°C Ambient Operating Temperature Range
- Device HBM Classification Level 2
- Device CDM Classification Level C4B
- System Voltage Range from 3.135 V to 5.25 V
- Low-Power Consumption
- 20 µA in Off Mode
- 90 µA in Sleep Mode With Two SMPSs Active
-
Four Step-Down Switched-Mode Power Supply (SMPS) Regulators:
- 0.7- to 3.3-V Output Range in 10- or 20-mV Steps
- Two SMPS Regulators With 3.5-A Capability, With the Ability to Combine into 7-A Output in Dual-Phase Configuration, With Differential Remote Sensing (Output and Ground)
- Two Other SMPS Regulators with 3-A and 1.5-A Capabilities
- Dynamic Voltage Scaling (DVS) Control and Output Current Measurement in 3.5-A and 3-A SMPS Regulators
- Hardware and Software Controlled Eco-mode™ Supplying up to 5 mA
- Short-Circuit Protection
- Power-Good Indication (Voltage and Overcurrent Indication)
- Internal Soft-Start for In-Rush Current Limitation
- Ability to Synchronize to External Clock between 1.7 MHz and 2.7 MHz
- Four Low-Dropout (LDO) Linear Regulators:
- 0 .9- to 3.3-V Output Range in 50-mV steps
- Two With 300-mA Capability and Bypass Mode
- One With 100-mA Capability and Capable of Low-Noise Performance up to 50 mA
- One LDO With 200-mA Current Capability
- Short-Circuit Protection
- 12-Bit Sigma-Delta General-Purpose ADC (GPADC) With 8 Input Channels (2 external)
- Thermal Monitoring With High Temperature Warning and Thermal Shutdown
- Power Sequence Control:
- Configurable Power-Up and Power-Down Sequences (OTP)
- Configurable Sequences Between the SLEEP and ACTIVE State Transition (OTP)
- Three Digital Output Signals that can be Included in the Startup Sequence
- Selectable Control Interface:
- One SPI for Resource Configurations and DVS Control
- Two
I2C Interfaces.
- One Dedicated for DVS Control
- One General Purpose I2C Interface for Resource Configuration and DVS Control
- OTP Bit-Integrity Error Detection With Options to Proceed or Hold Power-Up Sequence and RESET_OUT Release
- Package Option:
- 7-mm × 7-mm 48-pin With 0.5-mm Pitch
The TPS65919-Q1 PMIC integrates four configurable step-down converters with up to 3.5 A of output current to power the processor core, memory, I/O, and preregulation of LDOs The device is AEC-Q100 qualified. The step-down converters are synchronized to an internal 2.2-MHz clock to improve EMC performance of the device. The GPIO_3 pin allows the step-down converters to synchronize to an external clock, allowing multiple devices to synchronize to the same clock which improves system-level EMC performance. The device also contains four LDOs to power low-current or low-noise domains.
The power-sequence controller uses one-time programmable (OTP) memory to control the power sequences, as well as default configurations such as output voltage and GPIO configurations. The OTP is factory-programmed to allow start-up without any software required. Most static settings can be changed from the default through SPI or I2C to configure the device to meet many different system needs. For example, voltage-scaling registers are used to support dynamic voltage-scaling requirements of processors. The OTP also contains a bit-integrity-error detection feature to stop the power-up sequence if an error is detected, preventing the system from starting in an unknown state.
The TPS65919-Q1 device also includes an analog-to-digital converter (ADC) to monitor the system state. The GPADC includes two external channels to monitor any external voltage, as well as internal channels to measure supply voltage, output current, and die temperature, allowing the processor to monitor the health of the system. The device offers a watchdog to monitor for software lockup, and includes protection and diagnostic mechanisms such as short-circuit protection, thermal monitoring, shutdown, and automatic ADC conversions to detect if a voltage is below a predefined threshold. The PMIC can notify the processor of these events through the interrupt handler, allowing the processor to take action in response.
索取更多資訊
提供功能安全資訊。立即索取
您可能會感興趣的類似產品
針腳對針腳的功能與所比較的裝置相同。
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | TPS65919-Q1 Power Management Unit (PMU) for Processor datasheet (Rev. A) | PDF | HTML | 2018/8/20 | ||
| * | 使用指南 | TPS65919-Q1 Register Map | 2017/8/17 | |||
| 應用說明 | TPS6591x-Q1 Design Checklist (Rev. A) | 2021/5/6 | ||||
| 使用指南 | TPS65919-Q1 and TPS65917-Q1 User's Guide to Power DRA78x, and TDA3x (Rev. E) | 2019/3/13 | ||||
| 應用說明 | POR Generation in TPS65903x, TPS65917-Q1, TPS65919-Q1, and TPS65916 Devices (Rev. A) | 2018/9/21 | ||||
| 應用說明 | TPS65917 Power Estimation Tool (Rev. B) | 2018/6/14 | ||||
| 使用指南 | TPS65919-Q1 and TPS65917-Q1 User's Guide to Power DRA71x, DRA79x, and TDA2E-17 (Rev. E) | 2018/5/7 | ||||
| 應用說明 | Guide to Using the GPADC in TPS65903x, TPS65917-Q1, TPS65919-Q1, and TPS65916 de (Rev. A) | 2017/12/13 | ||||
| 功能安全資訊 | Safety Manual for TPS65919-Q1 Power Management Unit (PMU) | 2017/8/18 | ||||
| 應用說明 | Adaptive (Dynamic) Voltage (Frequency) Scaling – Motivation and Implementations | 2014/3/28 |
設計與開發
電源供應解決方案
探索包括 TPS65919-Q1 的解決方案。TI 提供適用於 TI 與非 TI 之系統單晶片 (SoC)、處理器、微控制器、感測器或現場可編程邏輯閘陣列 (FPGA) 的電源供應解決方案。
TPS65917EVM — TPS65917-Q1 電源管理 IC 評估模組
TPS65917-Q1 是一款針對汽車應用設計的整合式電源管理積體電路 (PMIC)。 該裝置提供五個可配置的降壓轉換器，每個輸出電流最高可達 3.5A，適用於記憶體供電、處理器核心電源、輸入/輸出 (I/O) 電源，或作為 LDO 的前級調整。 TPS65917-Q1 也包含 5 個供外部使用的 LDO。
TIDEP-0097 — 採用 Jacinto™ 6 入門級的入門級音響主機參考設計
此車用參考設計以 TI 的 Jacinto™ DRA71x 處理器為基礎，著重於節省系統級成本。其 6 層設計透過斷路方案最佳化、主要功能整合和配電網路最佳化降低 PCB 成本。可根據終端產品需求擴充或移除功能。此設計專為資訊娛樂和可重新設定的數位叢集等應用而設計，並支援 HDMI、USB3.0/2.0、TAS6424 數位 D 類放大器、FPD-Link 介面及多種其他功能。其中包含具單一 PMIC 的 12V 輸入。此外還隨附 Linux、Android 或 QNX 架構的軟體開發套件。
TIPA-050028 — 適用於汽車應用的 DRA78x 和 TDA3x 電源供應設計
此電源供應設計說明可為 DRA78x 或 TDA3x 供電的兩個最佳化電源管理 IC (PMIC)。使用指南針對使用 TPS65919-Q1 和 TPS65917-Q1 PMIC 的 DRA78x 和 TDA3x 處理器，詳細說明了電源設計的設計考量。
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| VQFN (RGZ) | 48 | Ultra Librarian |
訂購與品質
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。