TPS51916
- Synchronous Buck Controller (VDDQ)
- Conversion Voltage Range: 3 V to 28 V
- Output Voltage Range: 0.7 V to 1.8 V
- 0.8% VREF Accuracy
- Selectable Control
Architecture
- D-CAP™ Mode for Fast Transient Response
- D-CAP2™ Mode for Ceramic Output Capacitors
- Selectable 300 kHz, 400 kHz, 500 kHz, or 670 kHz Switching Frequencies
- Optimized Efficiency at Light and Heavy Loads with Auto-skip Function
- Supports Soft-Off in S4 and S5 States
- OCL/OVP/UVP/UVLO Protections
- Powergood Output
- 2-A LDO(VTT), Buffered Reference(VTTREF)
- 2-A (Peak) Sink and Source Current
- Buffered, Low Noise, 10-mA VTTREF Output
- 0.8% VTTREF, 20-mV VTT Accuracy
- Supports High-Z (S3) and Soft-Off (S4, S5)
- Thermal Shutdown
- 20-Pin, 3 mm × 3 mm, QFN Package
- Create a WEBENCH Design
The TPS51916 device provides a complete power supply for DDR2, DDR3, DDR3L, and DDR4 memory systems in the lowest total cost and minimum space. It integrates a synchronous buck regulator controller (VDDQ) with a 2-A sink and 2-A source tracking LDO (VTT) and buffered low noise reference (VTTREF).
The device employs D-CAP™ mode coupled with 300 kHz or 400 kHz frequencies for ease-of-use and fast transient response or D-CAP2™ mode coupled with higher 500 kHz or 670 kHz frequencies to support ceramic output capacitor without an external compensation circuit. The VTTREF tracks VDDQ/2 within excellent 0.8% accuracy. The VTT, which provides 2-A sink and 2-A source peak current capabilities, requires only 10-µF of ceramic capacitance. A dedicated LDO supply input is available.
The device also provides excellent power supply performance. It supports flexible power state control, placing VTT at high-Z in S3 and discharging VDDQ, VTT and VTTREF (soft-off) in S4 or S5 state. Programmable OCL with low-side MOSFET RDS(on) sensing, OVP, UVP, UVLO and thermal shutdown protections are also available.
.
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | TPS51916 Complete DDR2, DDR3, DDR3L and DDR4 Memory Power Solution Synchronous Buck Controller, 2-A LDO, Buffered Reference datasheet (Rev. F) | PDF | HTML | 2018/12/19 | ||
| 選擇指南 | Power Management Guide 2018 (Rev. R) | 2018/6/25 | ||||
| 更多文件說明 | Computing DDR DC-DC Power Solutions | 2012/8/22 |
設計與開發
如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。
TPS51916EVM-746 — 適用於 TPS51916 DDR2、DDR3 和 DDR3L 記憶體功率解決方案同步降壓控制器的評估模組
TIDA-00020 — Intel IMVP7 第二代 Core Mobile (Core i7) 電源管理參考設計
The Intel® Core i7 power management design is a reference design for the Intel® IMVP-7 Serial VID (SVID) power system. This design features an IMVP-7 3-phase CPU supply, a single-phase GPU Vcore supply, a 1.05-VCC IO supply, and a DDR3L/DDR4 memory rail. To greatly improve power (...)
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| WQFN (RUK) | 20 | Ultra Librarian |
訂購與品質
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。