TPS51100
- Input Voltage Range: 4.75 V to 5.25 V
- VLDOIN Voltage Range: 1.2 V to 3.6 V
- 3-A Sink/Source Termination Regulator
Includes Droop Compensation - Requires Only 20-μF Ceramic Output
Capacitance - Supports Hi-Z in S3 and Soft-Off in S5
- 1.2-V Input (VLDOIN) Helps Reduce Total
Power Dissipation - Integrated Divider Tracks 0.5 VDDQSNS for
VTT and VTTREF - Remote Sensing (VTTSNS)
- ±20-mV Accuracy for VTT and VTTREF
- 10-mA Buffered Reference (VTTREF)
- Built-In Soft-Start, UVLO, and OCL
- Thermal Shutdown
- Supports JEDEC Specifications
The TPS51100 is a 3-A, sink/source tracking termination regulator. The device is specifically designed for low-cost and low-external component count systems where space is a premium.
The TPS51100 maintains fast transient response, only requiring 20 µF (2 × 10 µF) of ceramic output capacitance. The TPS51100 supports remote sensing functions and all features required to power the DDR and DDR2 VTT bus termination according to the JEDEC specification. The part also supports DDR3 VTT termination with VDDQ at 1.5 V (typical). In addition, the TPS51100 includes integrated sleep-state controls, placing VTT in Hi-Z in S3 (suspend to RAM) and soft-off for VTT and VTTREF in S5 (suspend to disk). The TPS51100 is available in the thermally efficient 10-pin MSOP PowerPAD™ package and is specified from –40°C to 85°C.
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | TPS51100 3-A Sink / Source DDR Termination Regulator datasheet (Rev. E) | PDF | HTML | 2014/12/17 | ||
| 應用說明 | LDO Noise Demystified (Rev. B) | PDF | HTML | 2020/8/18 | |||
| 應用說明 | DDR VTT Power Solutions: A Competitive Analysis (Rev. A) | 2020/7/9 | ||||
| 選擇指南 | Power Management Guide 2018 (Rev. R) | 2018/6/25 | ||||
| 應用說明 | LDO PSRR Measurement Simplified (Rev. A) | PDF | HTML | 2017/8/9 | |||
| 使用指南 | Using the TPS51100 | 2004/7/13 |
設計與開發
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| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| HVSSOP (DGQ) | 10 | Ultra Librarian |
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