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TPS3850

現行

具有窗型監視計時器和可編程延遲功能且適用於 OV 和 UV 監控的精密窗型監控器

產品詳細資料

Rating Catalog Number of supplies monitored 1 Threshold voltage 1 (typ) (V) 0.372, 0.428, 1.116, 1.152, 1.248, 1.284, 1.674, 1.728, 1.872, 1.926, 2.79, 2.88, 3.069, 3.12, 3.168, 3.21, 3.432, 3.531, 4.65, 4.8, 5.2 Features Reset time delay, Separate VDD & sense, Timeout watchdog, Undervoltage and overvoltage monitor, Watchdog disable, Watchdog timer, Window watchdog Reset threshold accuracy (%) 0.8 Iq (typ) (mA) 0.01 Output driver type/reset output Active-low, Open-drain Time delay (ms) 10, 200 Watchdog timer WDI (s) Programmable Supply voltage (min) (V) 1.6 Supply voltage (max) (V) 6.5 Operating temperature range (°C) -40 to 125
Rating Catalog Number of supplies monitored 1 Threshold voltage 1 (typ) (V) 0.372, 0.428, 1.116, 1.152, 1.248, 1.284, 1.674, 1.728, 1.872, 1.926, 2.79, 2.88, 3.069, 3.12, 3.168, 3.21, 3.432, 3.531, 4.65, 4.8, 5.2 Features Reset time delay, Separate VDD & sense, Timeout watchdog, Undervoltage and overvoltage monitor, Watchdog disable, Watchdog timer, Window watchdog Reset threshold accuracy (%) 0.8 Iq (typ) (mA) 0.01 Output driver type/reset output Active-low, Open-drain Time delay (ms) 10, 200 Watchdog timer WDI (s) Programmable Supply voltage (min) (V) 1.6 Supply voltage (max) (V) 6.5 Operating temperature range (°C) -40 to 125
VSON (DRC) 10 9 mm² 3 x 3
  • Input voltage range: VDD = 1.6 V to 6.5 V
  • 0.8% Voltage threshold accuracy
  • Low supply current: IDD = 10 µA (typical)
  • User-programmable watchdog timeout
  • User-programmable reset delay
  • Factory-programmed precision watchdog and reset timers
  • Open-drain outputs
  • Precision over- and undervoltage monitoring:
    • Supports common rails from 0.9 V to 5.0 V
    • ±4% and ±7% Fault windows available
    • 0.5% Hysteresis
  • Watchdog disable feature
  • Available in a small 3-mm × 3-mm, 10-Pin VSON package
  • Junction operating temperature range: –40°C to +125°C
  • Input voltage range: VDD = 1.6 V to 6.5 V
  • 0.8% Voltage threshold accuracy
  • Low supply current: IDD = 10 µA (typical)
  • User-programmable watchdog timeout
  • User-programmable reset delay
  • Factory-programmed precision watchdog and reset timers
  • Open-drain outputs
  • Precision over- and undervoltage monitoring:
    • Supports common rails from 0.9 V to 5.0 V
    • ±4% and ±7% Fault windows available
    • 0.5% Hysteresis
  • Watchdog disable feature
  • Available in a small 3-mm × 3-mm, 10-Pin VSON package
  • Junction operating temperature range: –40°C to +125°C

The TPS3850 combines a precision voltage supervisor with a programmable window watchdog timer. The TPS3850 window comparator achieves 0.8% accuracy (–40°C to +125°C) for both overvoltage (VIT+(OV)) and undervoltage (VIT–(UV)) thresholds on the SENSE pin. The TPS3850 also includes accurate hysteresis on both thresholds, making the device ideal for use with tight tolerance systems. The supervisor RESET delay can be set by factory-programmed default delay settings, or programmed by an external capacitor. The factory-programmed RESET delay features a 9.5% accuracy, high-precision delay timing.

The TPS3850 includes a programmable window watchdog timer for a wide variety of applications. The dedicated watchdog output ( WDO) enables increased resolution to help determine the nature of fault conditions. The window watchdog timeouts can be set by factory-programmed default delay settings, or programmed by an external capacitor. The watchdog can be disabled via logic pins to avoid undesired watchdog timeouts during the development process.

The TPS3850 is available in a small 3.00-mm × 3.00-mm, 10-pin VSON package.

The TPS3850 combines a precision voltage supervisor with a programmable window watchdog timer. The TPS3850 window comparator achieves 0.8% accuracy (–40°C to +125°C) for both overvoltage (VIT+(OV)) and undervoltage (VIT–(UV)) thresholds on the SENSE pin. The TPS3850 also includes accurate hysteresis on both thresholds, making the device ideal for use with tight tolerance systems. The supervisor RESET delay can be set by factory-programmed default delay settings, or programmed by an external capacitor. The factory-programmed RESET delay features a 9.5% accuracy, high-precision delay timing.

The TPS3850 includes a programmable window watchdog timer for a wide variety of applications. The dedicated watchdog output ( WDO) enables increased resolution to help determine the nature of fault conditions. The window watchdog timeouts can be set by factory-programmed default delay settings, or programmed by an external capacitor. The watchdog can be disabled via logic pins to avoid undesired watchdog timeouts during the development process.

The TPS3850 is available in a small 3.00-mm × 3.00-mm, 10-pin VSON package.

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技術文件

star =TI 所選的此產品重要文件
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類型 標題 日期
* Data sheet TPS3850 Precision Voltage Supervisor with Programmable Window Watchdog Timer datasheet (Rev. B) PDF | HTML 2021年 9月 9日
Application note Voltage Supervisors (Reset ICs): Frequently Asked Questions (FAQs) (Rev. A) 2020年 3月 17日
E-book Voltage Supervisor and Reset ICs: Tips, Tricks and Basics 2019年 6月 28日
Application note Comparing Voltage and Processor Monitoring Solutions 2019年 4月 5日
Application note How Comparator Topology Influences Propagation Delay 2017年 4月 5日
Technical article Exploring watchdog timer applications PDF | HTML 2017年 2月 2日

設計與開發

如需其他條款或必要資源,請按一下下方的任何標題以檢視詳細頁面 (如有)。

開發板

TPS3850EVM-781 — 具有視窗看門狗計時器的 TPS3850 高準確度監控器評估模組

TPS3850EVM-781 評估模組 (EVM) 採用典型配置設計,用於評估 TPS3850 低靜態電流 (Iq)、0.8% 準確度、具整合式監視定時器之監控器的運作與性能。
使用指南: PDF
TI.com 無法提供
模擬型號

TPS3850 PSpice Transient Model (Rev. A)

SBVM649A.ZIP (67 KB) - PSpice Model
模擬型號

TPS3850 Unencrypted PSpice Transient Model (Rev. A)

SBVM648A.ZIP (9 KB) - PSpice Model
模擬工具

PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具

PSpice® for TI 是有助於評估類比電路功能的設計和模擬環境。這款全功能設計和模擬套件使用 Cadence® 的類比分析引擎。PSpice for TI 包括業界最大的模型庫之一,涵蓋我們的類比和電源產品組合,以及特定類比行為模型,且使用無需支付費用。

PSpice for TI 設計和模擬環境可讓您使用其內建函式庫來模擬複雜的混合訊號設計。在進行佈局和製造之前,建立完整的終端設備設計和解決方案原型,進而縮短上市時間並降低開發成本。 

在 PSpice for TI 設計與模擬工具中,您可以搜尋 TI (...)
參考設計

TIDA-01589 — 具備雜訊消除與回波抵銷功能的高保真、近場雙向音訊參考設計

人機互動需要聲學介面,以提供全雙工免手持通訊。在免手持模式下,來自喇叭的部分遠端或近端音訊訊號會耦合至麥克風。此外,在雜訊環境中,除了可擷取有用的近端音訊訊號外,麥克風還會擷取環境雜訊。擷取的多麥克風音訊訊號會受到聲學背景雜訊及回波訊號破壞,這些訊號會大幅降低所需訊號的清晰度,並限制後續音訊處理系統的性能。此參考設計展示了雙麥克風,其用於透過立體聲 ADC 實現音訊輸入,透過低功耗 DSP 執行雜訊降低、聲音回波消除和其他音訊品質強化演算法。此設計還採用了 TI 智慧型放大器技術,可透過微型喇叭實現高品質、高 SPL 音訊輸出。
Design guide: PDF
電路圖: PDF
封裝 針腳 CAD 符號、佔位空間與 3D 模型
VSON (DRC) 10 Ultra Librarian

訂購與品質

內含資訊:
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  • REACH
  • 產品標記
  • 鉛塗層/球物料
  • MSL 等級/回焊峰值
  • MTBF/FIT 估算值
  • 材料內容
  • 認證摘要
  • 進行中持續性的可靠性監測
內含資訊:
  • 晶圓廠位置
  • 組裝地點

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