TMS320C6742

現行

低功耗 C674x 浮點 DSP- 200MHz

立即訂購

產品規格表

document-pdfAcrobat TMS320C6742 Fixed- and Floating-Point DSP datasheet (Rev. F) (英文) PDF | HTML

使用指南

document-pdfAcrobat
TMS320C6742 DSP Technical Reference Manual (Rev. C) (英文)

TMS320C6742

現行

立即訂購

產品詳細資料

CPU

32-/64-bit

Frequency (MHz)

200

Features

1 RTC, 3 enhanced-capture peripherals

Operating system

SYS/BIOS

Security

Secure boot

Rating

Catalog

Operating temperature range (°C)

-40 to 105

CPU

32-/64-bit

Frequency (MHz)

200

Features

1 RTC, 3 enhanced-capture peripherals

Operating system

SYS/BIOS

Security

Secure boot

Rating

Catalog

Operating temperature range (°C)

-40 to 105

NFBGA (ZWT)

361

256 mm² (16 mm × 16 mm)

200-MHz C674x Fixed- and Floating-Point VLIW DSP
C674x Instruction Set Features
- Superset of the C67x+ and C64x+ ISAs
- Up to 1600 MIPS and 1200 MFLOPS
- Byte-Addressable (8-, 16-, 32-, and 64-Bit Data)
- 8-Bit Overflow Protection
- Bit-Field Extract, Set, Clear
- Normalization, Saturation, Bit-Counting
- Compact 16-Bit Instructions
C674x Two-Level Cache Memory Architecture
- 32KB of L1P Program RAM/Cache
- 32KB of L1D Data RAM/Cache
- 64KB of L2 Unified Mapped RAM/Cache
- Flexible RAM/Cache Partition (L1 and L2)
Enhanced Direct Memory Access Controller 3 (EDMA3):
- 2 Channel Controllers
- 3 Transfer Controllers
- 64 Independent DMA Channels
- 16 Quick DMA Channels
- Programmable Transfer Burst Size
TMS320C674x Floating-Point VLIW DSP Core
- Load-Store Architecture With Nonaligned Support
- 64 General-Purpose Registers (32-Bit)
- Six ALU (32- and 40-Bit) Functional Units
  - Supports 32-Bit Integer, SP (IEEE Single Precision/32-Bit) and DP (IEEE Double Precision/64-Bit) Floating Point
  - Supports up to Four SP Additions Per Clock, Four DP Additions Every Two Clocks
  - Supports up to Two Floating-Point (SP or DP) Reciprocal Approximation (RCPxP) and Square-Root Reciprocal Approximation (RSQRxP) Operations Per Cycle
- Two Multiply Functional Units:
  - Mixed-Precision IEEE Floating-Point Multiply Supported up to:
    - 2 SP × SP → SP Per Clock
    - 2 SP × SP → DP Every Two Clocks
    - 2 SP × DP → DP Every Three Clocks
    - 2 DP × DP → DP Every Four Clocks
  - Fixed-Point Multiply Supports Two 32 × 32-Bit Multiplies, Four 16 × 16-Bit Multiplies, or Eight 8 × 8-Bit Multiplies per Clock Cycle, and Complex Multiples
- Instruction Packing Reduces Code Size
- All Instructions Conditional
- Hardware Support for Modulo Loop Operation
- Protected Mode Operation
- Exceptions Support for Error Detection and Program Redirection
Software Support
- TI DSPBIOS
- Chip Support Library and DSP Library
1.8-V or 3.3-V LVCMOS I/Os (Except for DDR2 Interfaces)
Two External Memory Interfaces:
- EMIFA
  - NOR (8- or 16-Bit-Wide Data)
  - NAND (8- or 16-Bit-Wide Data)
  - 16-Bit SDRAM With 128-MB Address Space
- DDR2/Mobile DDR Memory Controller With one of the Following:
  - 16-Bit DDR2 SDRAM With 256-MB Address Space
  - 16-Bit mDDR SDRAM With 256-MB Address Space
One Configurable 16550-Type UART Module:
- With Modem Control Signals
- 16-Byte FIFO
- 16x or 13x Oversampling Option
One Serial Peripheral Interface (SPI) With Multiple Chip Selects
Two Master and Slave Inter-Integrated Circuits
(I²C Bus™)
One Host-Port Interface (HPI) With 16-Bit-Wide Muxed Address and Data Bus For High Bandwidth
One Multichannel Audio Serial Port (McASP):
- Two Clock Zones and 16 Serial Data Pins
- Supports TDM, I2S, and Similar Formats
- DIT-Capable
- FIFO Buffers for Transmit and Receive
One Multichannel Buffered Serial Port (McBSPs):
- Supports TDM, I2S, and Similar Formats
- AC97 Audio Codec Interface
- Telecom Interfaces (ST-Bus, H100)
- 128-Channel TDM
- FIFO Buffers for Transmit and Receive
Real-Time Clock (RTC) With 32-kHz Oscillator and Separate Power Rail
One 64-Bit General-Purpose Timer (Configurable as Two 32-Bit Timers)
One 64-Bit General-Purpose or Watchdog Timer (Configurable as Two 32-Bit General-Purpose Timers)
Two Enhanced High-Resolution Pulse Width Modulators (eHRPWMs):
- Dedicated 16-Bit Time-Base Counter With Period and Frequency Control
- 6 Single-Edge Outputs, 6 Dual-Edge Symmetric Outputs, or 3 Dual-Edge Asymmetric Outputs
- Dead-Band Generation
- PWM Chopping by High-Frequency Carrier
- Trip Zone Input
Three 32-Bit Enhanced Capture (eCAP) Modules:
- Configurable as 3 Capture Inputs or 3 Auxiliary Pulse Width Modulator (APWM) Outputs
- Single-Shot Capture of up to Four Event Timestamps
Packages:
- 361-Ball Pb-Free Plastic Ball Grid Array (PBGA) [ZCE Suffix], 0.65-mm Ball Pitch
- 361-Ball Pb-Free PBGA [ZWT Suffix],
  0.80-mm Ball Pitch
Commercial or Extended Temperature

All trademarks are the property of their respective owners.

200-MHz C674x Fixed- and Floating-Point VLIW DSP
C674x Instruction Set Features
- Superset of the C67x+ and C64x+ ISAs
- Up to 1600 MIPS and 1200 MFLOPS
- Byte-Addressable (8-, 16-, 32-, and 64-Bit Data)
- 8-Bit Overflow Protection
- Bit-Field Extract, Set, Clear
- Normalization, Saturation, Bit-Counting
- Compact 16-Bit Instructions
C674x Two-Level Cache Memory Architecture
- 32KB of L1P Program RAM/Cache
- 32KB of L1D Data RAM/Cache
- 64KB of L2 Unified Mapped RAM/Cache
- Flexible RAM/Cache Partition (L1 and L2)
Enhanced Direct Memory Access Controller 3 (EDMA3):
- 2 Channel Controllers
- 3 Transfer Controllers
- 64 Independent DMA Channels
- 16 Quick DMA Channels
- Programmable Transfer Burst Size
TMS320C674x Floating-Point VLIW DSP Core
- Load-Store Architecture With Nonaligned Support
- 64 General-Purpose Registers (32-Bit)
- Six ALU (32- and 40-Bit) Functional Units
  - Supports 32-Bit Integer, SP (IEEE Single Precision/32-Bit) and DP (IEEE Double Precision/64-Bit) Floating Point
  - Supports up to Four SP Additions Per Clock, Four DP Additions Every Two Clocks
  - Supports up to Two Floating-Point (SP or DP) Reciprocal Approximation (RCPxP) and Square-Root Reciprocal Approximation (RSQRxP) Operations Per Cycle
- Two Multiply Functional Units:
  - Mixed-Precision IEEE Floating-Point Multiply Supported up to:
    - 2 SP × SP → SP Per Clock
    - 2 SP × SP → DP Every Two Clocks
    - 2 SP × DP → DP Every Three Clocks
    - 2 DP × DP → DP Every Four Clocks
  - Fixed-Point Multiply Supports Two 32 × 32-Bit Multiplies, Four 16 × 16-Bit Multiplies, or Eight 8 × 8-Bit Multiplies per Clock Cycle, and Complex Multiples
- Instruction Packing Reduces Code Size
- All Instructions Conditional
- Hardware Support for Modulo Loop Operation
- Protected Mode Operation
- Exceptions Support for Error Detection and Program Redirection
Software Support
- TI DSPBIOS
- Chip Support Library and DSP Library
1.8-V or 3.3-V LVCMOS I/Os (Except for DDR2 Interfaces)
Two External Memory Interfaces:
- EMIFA
  - NOR (8- or 16-Bit-Wide Data)
  - NAND (8- or 16-Bit-Wide Data)
  - 16-Bit SDRAM With 128-MB Address Space
- DDR2/Mobile DDR Memory Controller With one of the Following:
  - 16-Bit DDR2 SDRAM With 256-MB Address Space
  - 16-Bit mDDR SDRAM With 256-MB Address Space
One Configurable 16550-Type UART Module:
- With Modem Control Signals
- 16-Byte FIFO
- 16x or 13x Oversampling Option
One Serial Peripheral Interface (SPI) With Multiple Chip Selects
Two Master and Slave Inter-Integrated Circuits
(I²C Bus™)
One Host-Port Interface (HPI) With 16-Bit-Wide Muxed Address and Data Bus For High Bandwidth
One Multichannel Audio Serial Port (McASP):
- Two Clock Zones and 16 Serial Data Pins
- Supports TDM, I2S, and Similar Formats
- DIT-Capable
- FIFO Buffers for Transmit and Receive
One Multichannel Buffered Serial Port (McBSPs):
- Supports TDM, I2S, and Similar Formats
- AC97 Audio Codec Interface
- Telecom Interfaces (ST-Bus, H100)
- 128-Channel TDM
- FIFO Buffers for Transmit and Receive
Real-Time Clock (RTC) With 32-kHz Oscillator and Separate Power Rail
One 64-Bit General-Purpose Timer (Configurable as Two 32-Bit Timers)
One 64-Bit General-Purpose or Watchdog Timer (Configurable as Two 32-Bit General-Purpose Timers)
Two Enhanced High-Resolution Pulse Width Modulators (eHRPWMs):
- Dedicated 16-Bit Time-Base Counter With Period and Frequency Control
- 6 Single-Edge Outputs, 6 Dual-Edge Symmetric Outputs, or 3 Dual-Edge Asymmetric Outputs
- Dead-Band Generation
- PWM Chopping by High-Frequency Carrier
- Trip Zone Input
Three 32-Bit Enhanced Capture (eCAP) Modules:
- Configurable as 3 Capture Inputs or 3 Auxiliary Pulse Width Modulator (APWM) Outputs
- Single-Shot Capture of up to Four Event Timestamps
Packages:
- 361-Ball Pb-Free Plastic Ball Grid Array (PBGA) [ZCE Suffix], 0.65-mm Ball Pitch
- 361-Ball Pb-Free PBGA [ZWT Suffix],
  0.80-mm Ball Pitch
Commercial or Extended Temperature

All trademarks are the property of their respective owners.

The TMS320C6742 fixed- and floating-point DSP is a low-power applications processor based on a C674x DSP core. This DSP provides significantly lower power than other members of the TMS320C6000™ platform of DSPs.

The device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs) to quickly bring to market devices with robust operating systems, rich user interfaces, and high processor performance through the maximum flexibility of a fully integrated, mixed processor solution.

The device DSP core uses a 2-level cache-based architecture. The level 1 program cache (L1P) is a
32-KB direct mapped cache, and the level 1 data cache (L1D) is a 32-KB 2-way, set-associative cache. The level 2 program cache (L2P) consists of a 64-KB memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two.

The peripheral set includes: one I²C Bus interface; one multichannel audio serial port (McASP) with 16 serializers and FIFO buffers; one multichannel buffered serial port (McBSP) with FIFO buffers; one serial peripheral interface (SPI) with multiple chip selects; two 64-bit general-purpose timers each configurable (one configurable as a watchdog); a configurable 16-bit host-port interface (HPI); up to 9 banks of general-purpose input/output (GPIO) pins, with each bank containing 16 pins with programmable interrupt and event generation modes, multiplexed with other peripherals; one UART interface (with RTS and CTS); two enhanced high-resolution pulse width modulator (eHRPWM) peripherals; three 32-bit enhanced capture (eCAP) module peripherals which can be configured as 3 capture inputs or 3 APWM outputs; two external memory interfaces: an asynchronous and SDRAM external memory interface (EMIFA) for slower memories or peripherals; and a higher speed DDR2/Mobile DDR controller.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each peripheral, see the related sections in this document and the associated peripheral reference guides.

The device has a complete set of development tools for the DSP. These tools include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows debugger interface for visibility into source code execution.

The TMS320C6742 fixed- and floating-point DSP is a low-power applications processor based on a C674x DSP core. This DSP provides significantly lower power than other members of the TMS320C6000™ platform of DSPs.

The device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs) to quickly bring to market devices with robust operating systems, rich user interfaces, and high processor performance through the maximum flexibility of a fully integrated, mixed processor solution.

The device DSP core uses a 2-level cache-based architecture. The level 1 program cache (L1P) is a
32-KB direct mapped cache, and the level 1 data cache (L1D) is a 32-KB 2-way, set-associative cache. The level 2 program cache (L2P) consists of a 64-KB memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two.

The peripheral set includes: one I²C Bus interface; one multichannel audio serial port (McASP) with 16 serializers and FIFO buffers; one multichannel buffered serial port (McBSP) with FIFO buffers; one serial peripheral interface (SPI) with multiple chip selects; two 64-bit general-purpose timers each configurable (one configurable as a watchdog); a configurable 16-bit host-port interface (HPI); up to 9 banks of general-purpose input/output (GPIO) pins, with each bank containing 16 pins with programmable interrupt and event generation modes, multiplexed with other peripherals; one UART interface (with RTS and CTS); two enhanced high-resolution pulse width modulator (eHRPWM) peripherals; three 32-bit enhanced capture (eCAP) module peripherals which can be configured as 3 capture inputs or 3 APWM outputs; two external memory interfaces: an asynchronous and SDRAM external memory interface (EMIFA) for slower memories or peripherals; and a higher speed DDR2/Mobile DDR controller.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each peripheral, see the related sections in this document and the associated peripheral reference guides.

The device has a complete set of development tools for the DSP. These tools include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows debugger interface for visibility into source code execution.

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TI 提供有限的設計支援

使用此產品的現有專案具備有限的 TI 設計支援。若有提供，您可在此頁面找到相關資訊、工具和軟體。使用此產品的現有設計具備有限的 TI 設計支援。在 TI E2E™ 支援論壇中申請有限的設計支援。

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重要文件	類型	標題	格式選項
*	資料表	TMS320C6742 Fixed- and Floating-Point DSP datasheet (Rev. F)	PDF \| HTML	2017/1/31
*	使用指南	TMS320C6742 DSP Technical Reference Manual (Rev. C)		2016/9/12
*	勘誤表	TMS320C6742 Fixed- and Floating-Point DSP (Revs 2.3, 2.1, 2.0, 1.1 & 1.0) (Rev. H)		2014/3/21
	應用說明	How to Migrate CCS 3.x Projects to the Latest CCS (Rev. A)	PDF \| HTML	2021/5/19
	應用說明	OMAPL138/C6748 ROM Bootloader Resources and FAQ (Rev. A)	PDF \| HTML	2021/1/21
	使用指南	SYS/BIOS (TI-RTOS Kernel) User's Guide (Rev. V)		2020/6/1
	應用說明	Programming mDDR/DDR2 EMIF on OMAP-L1x/C674x		2019/12/20
	使用指南	L138/C6748 development kit (LCDK) (Rev. A)	PDF \| HTML	2019/9/18
	應用說明	Using DSPLIB FFT Implementation for Real Input and Without Data Scaling	PDF \| HTML	2019/6/11
	應用說明	Programming PLL Controllers on OMAP-L1x8/C674x/AM18xx	PDF \| HTML	2019/4/25
	應用說明	TMS320C6748/46/42 power consumption summary	PDF \| HTML	2019/3/26
	應用說明	General Hardware Design/BGA PCB Design/BGA	PDF \| HTML	2019/2/22
	應用說明	OMAP-L13x / C674x / AM1x schematic review guidelines	PDF \| HTML	2019/2/14
	應用說明	McASP Design Guide - Tips, Tricks, and Practical Examples		2019/1/10
	應用說明	Processor SDK RTOS Audio Benchmark Starter Kit		2017/4/12
	應用說明	TI DSP Benchmarking	PDF \| HTML	2016/1/13
	應用說明	Using the TMS320C6748/C6746/C6742 Bootloader (Rev. F)		2014/1/23
	使用指南	System Analyzer User's Guide (Rev. F)		2013/11/18
	應用說明	OMAP-L132/L138, TMS320C6742/6/8 Pin Multiplexing Utility (Rev. B)		2013/9/27
	應用說明	Powering the TMS320C6742, TMS320C6746, and TMS320C6748 With the TPS650061		2011/12/19
	應用說明	Introduction to TMS320C6000 DSP Optimization		2011/10/6
	使用指南	TMS320C674x/OMAP-L1x Processor Peripherals Overview Reference Guide (Rev. F)		2011/9/14
	應用說明	Medium Integrated Power Solution Using a Dual DC/DC Converter and an LDO (Rev. B)		2011/8/29
	應用說明	Simple Power Solution Using LDOs (Rev. B)		2011/8/29
	應用說明	High-Vin, High-Efficiency Power Solution Using DC/DC Converter With DVFS (Rev. C)		2011/8/29
	白皮書	Software and Hardware Design Challenges Due to Dynamic Raw NAND Market		2011/5/19
	使用指南	TMS320C674x DSP Megamodule Reference Guide (Rev. A)		2010/8/3
	使用指南	TMS320C674x DSP CPU and Instruction Set User's Guide (Rev. B)		2010/7/30
	應用說明	High-Efficiency Power Solution Using DC/DC Converters With DVFS (Rev. A)		2010/5/5
	應用說明	High-Integration, High-Efficiency Power Solution Using DC/DC Converters w/DVFS (Rev. A)		2010/5/5
	應用說明	TMS320C6748/46/42 & OMAP-L1x8 USB Upstream Device Compliance Testing		2009/8/17
	應用說明	TMS320C6748/46/42 & OMAP-L132/L138 USB Downstream Host Compliance Testing		2009/8/17
	應用說明	TMS320C6748/46/42 Complementary Products		2009/7/20
	白皮書	Efficient Fixed- and Floating-Point Code Execution on the TMS320C674x Core		2009/6/24
	應用說明	TMS320C674x/OMAP-L1x USB Compliance Checklist		2009/3/12
	使用指南	TMS320C674x DSP Cache User's Guide (Rev. A)		2009/2/11

設計與開發

電源供應解決方案

為 TMS320C6742 尋找可用的電源供應解決方案。TI 提供適用於 TI 與非 TI 之系統單晶片 (SoC)、處理器、微控制器、感測器或現場可編程邏輯閘陣列 (FPGA) 的電源供應解決方案。

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開發套件

TMDSLCDK138 — OMAP-L138 開發套件 (LCDK)

OMAP-L138 DSP + Arm9™ 開發套件可實現快速且簡便的 Linux 軟體與硬體開發。此可擴展平臺將簡化並加速日常應用中軟體與硬體的開發，這些應用需要即時訊號處理與控制功能，包括工業控制、醫療診斷與通訊。這套低成本套件附有可自由下載與複製的電路圖與設計檔案，大幅減少設計工作量。多種標準連接與儲存介面可供選擇，使開發人員能輕鬆將音訊、影像與其他訊號引入電路板。擴充接頭（如 LCD 螢幕擴充接頭與 Leopard Imaging 的相機感測器）可讓客戶擴展電路板的功能。

LCDK 不具備內建模擬器。開始開發時需使用來自 TI 的外部模擬器（例如 XDS100、XDS200、 (...)

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開發套件

TMDSLCDK6748 — TMS320C6748 DSP 開發套件 (LCDK)

TMS320C6748 DSP 開發套件 (LCDK) 是可擴充的平台，打破需要嵌入式分析和即時訊號處理（包括生物辨識分析、通訊及音訊）的應用程式開發障礙。低成本 LCDK 還可加快並簡化即時 DSP 應用程式的硬體開發。這項全新電路板可免費下載和複製電路板電路圖與設計檔案，減少設計工作量。多種標準的連接與儲存介面，可讓您輕鬆將音訊、視訊及其他訊號引入電路板。

LCDK 不具備內建模擬器。開始開發時需使用來自 TI 或第三方的外部模擬器。

TMDSLCDK6748 以相同的性能、價格與功能取代 TMDXLCDK6748。該產品以限量方式供應，隨庫存逐步增加。

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偵錯探測器

TMDSEMU200-U — XDS200 USB 偵錯探測器

XDS200 是為 TI 嵌入式裝置偵錯的偵錯探測器（模擬器）。對於大多數裝置，建議使用較新、成本較低的 XDS110 (www.ti.com/tool/TMDSEMU110-U)。XDS200 支援單一 Pod 中廣泛的標準（IEEE1149.1、IEEE1149.7、SWD）。所有 XDS 偵錯探針在所有配備嵌入式追蹤緩衝器 (ETB) 的 Arm® 與 DSP 處理器中均支援核心與系統追蹤。

XDS200 透過 TI 20 接腳連接器（配備適用 TI 14 接腳、Arm Cortex® 10 接腳和 Arm 20 接腳的多重轉接器）連接到目標電路板，並透過 USB2.0 高速 (...)

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偵錯探測器

TMDSEMU560V2STM-U — XDS560™ 軟體 v2 系統追蹤 USB 偵錯探測器

XDS560v2 是 XDS560™ 系列偵錯探測器中性能最高的，且同時支援傳統 JTAG 標準 (IEEE1149.1) 與 cJTAG (IEEE1149.7)。請注意，其不支援序列線偵錯 (SWD)。

所有 XDS 偵錯探測器均在所有配備嵌入式追蹤緩衝器 (ETB) 的 ARM 與 DSP 處理器中支援核心與系統追蹤。對於針腳上的追蹤，則需要 XDS560v2 PRO TRACE。

XDS560v2 透過 MIPI HSPT 60 針腳接頭 (具有用於 TI 14 針腳、TI 20 針腳和 ARM 20 針腳的多轉接器) 連接到目標電路板，並透過 USB2.0 高速 (...)

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偵錯探測器

TMDSEMU560V2STM-UE — XDS560v2 System Trace USB 與乙太網路偵錯探測器

The XDS560v2 is the highest performance of the XDS560™ family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors (...)

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偵錯探測器

LB-3P-TRACE32-DSP — 適用於數位訊號處理器 (DSP) 的 Lauterbach TRACE32 偵錯和追蹤系統

Lauterbach‘s TRACE32® tools are a suite of leading-edge hardware and software components that enables developers to analyze, optimize and certify all kinds of single- or multi-core Digital Signal processors (DSPs) which are a popular choice for audio and video processing as well as radar data (...)

從：Lauterbach GmbH

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檢視選項

軟體開發套件 (SDK)

PROCESSOR-SDK-C6748 — 適用於 C6748 處理器的處理器 SDK - 支援 TI-RTOS

處理器 SDK (軟體開發套件) 是一套專為 TI 嵌入式處理器所設計的整合軟體平台，提供簡易設定，可迅速且立即執行基準測試與示範。所有 TI 代表產品的處理器 SDK 版本均相同，開發人員能順暢地在其他裝置上再次使用軟體，與移轉軟體至其他裝置。有了處理器 SDK 和 TI 嵌入式處理器解決方案，讓開發可調式平台解決方案從此變得更輕鬆簡單。

C6748、C6746 和 C6742 的處理器 SDK 包含對 TI-RTOS 作業系統的支援。

RTOS 主要特點：

TI-RTOS 核心、這是一套適用於 TI 裝置的輕量即時嵌入式作業系統
晶片支援函式庫、驅動程式和基礎電路板支援公用程式
最佳化 (...)

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軟體開發套件 (SDK)

PROCESSOR-SDK-RTOS-OMAPL138 — TI-RTOS Processor SDK for OMAP-L138, OMAP-L132 and C6748, C6746, C6742 (No design support from TI available. Refer to Overview- RTOS Highlights for details.)

處理器 SDK (軟體開發套件) 是一套專為 TI 嵌入式處理器所設計的整合軟體平台，提供簡易設定，可迅速且立即執行基準測試與示範。所有 TI 代表產品的處理器 SDK 版本均相同，開發人員能順暢地在其他裝置上再次使用軟體，與移轉軟體至其他裝置。有了處理器 SDK 和 TI 嵌入式處理器解決方案，讓開發可調式平台解決方案從此變得更輕鬆簡單。

處理器 SDK 包括對 Linux 與 TI-RTOS 作業系統的支援。

Linux 主要特點：

長期穩定 (LTS) Mainline Linux 核心支援
U-Boot 開機載入程式支援
Yocto Project™ OE Core 相容檔案系統

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IDE、配置、編譯器或偵錯程式

CCSTUDIO — Code Composer Studio™ integrated development environment (IDE)

CCStudio™ IDE is part of TI's extensive CCStudio™ development ecosystem and is an integrated development environment for TI's microcontrollers, processors, wireless connectivity devices, and radar sensors. CCStudio IDE is available as desktop or cloud-based applications. The cloud version (...)

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驅動程式或資料庫

MATHLIB — 用於浮點裝置的 DSP 數學函式庫

The Texas Instruments math library is an optimized floating-point math function library for C programmers using TI floating point devices. These routines are typically used in computationally intensive real-time applications where optimal execution speed is critical. By using these routines instead (...)

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驅動程式或資料庫

SPRC264 — TMS320C5000/6000 映像庫 (IMGLIB)

C5000 6000 影像處理庫 (IMGLIB) 是適合 C 程式設計工具的最佳化影像/影片處理函式庫。此函式庫包括 C 可呼叫通用影像/影片處理常式，這些常式通常用於運算密集型即時應用。相較於同等標準 ANSI C 語言程式碼，使用這些常式可以實現更高性能。IMGLIB 透過立即可用的 DSP 功能與原始程式碼，能夠大幅縮短應用程式開發時間。

查看基準測試：DSP 核心基準測試

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驅動程式或資料庫

SPRC265 — TMS320C6000 DSP 函式庫 (DSPLIB)

TMS320C6000 數位訊號處理器函式庫 (DSPLIB) 是適合 C 編程人員的平台最佳化 DSP 函式庫。此函式庫包括可呼叫 C 語言的通用訊號處理常式，通常用於運算密集的即時應用。相較於同等標準 ANSI C 語言程式碼，使用這些常式可以實現更高性能。DSPLIB 透過立即可用的 DSP 功能與原始程式碼，能夠大幅縮短應用程式開發時間。

查看基準測試：DSP 核心基準測試

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驅動程式或資料庫

TELECOMLIB — 電信和媒體庫 - 用於 TMS320C64x+ 和 TMS320C55x 處理器的 FAXLIB、VoLIB 和 AEC/AER

Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be (...)

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軟體轉碼器

ADT-3P-DSPVOIPCODECS — 適應性數位技術 DSP VOIP、語音和音訊轉碼器

Adaptive Digital is a developer of voice quality enhancement algorithms, and best-in-class acoustic echo cancellation software that work with TI DSPs. Adaptive Digital has extensive experience in the algorithm development, implementation, optimization and configuration tuning. They provide (...)

從：Adaptive Digital Technologies, Inc.

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