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TMS320C5517

現行

低功耗 C55x 定點 DSP - 高達 200MHz、USB、LCD 介面、FFT HWA、SAR ADC

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產品規格表

TMS320C5517

現行
立即訂購

產品詳細資料

CPU 16-bit Frequency (MHz) 75, 200 Hardware accelerators FFT Coprocessor Operating system DSP/BIOS, VLX Rating Catalog Operating temperature range (°C) -40 to 85
CPU 16-bit Frequency (MHz) 75, 200 Hardware accelerators FFT Coprocessor Operating system DSP/BIOS, VLX Rating Catalog Operating temperature range (°C) -40 to 85
NFBGA (ZCH) 196 100 mm² (10 mm × 10 mm)
  • CORE:
    • High-Performance, Low-Power, TMS320C55x Fixed-Point Digital Signal Processor
      • 13.33- to 5-ns Instruction Cycle Time
      • 75- to 200-MHz Clock Rate
      • One or Two Instructions Executed per Cycle
      • Dual Multiply-and-Accumulate Units (Up to 450 Million Multiply-Accumulates per Second [MMACS])
      • Two Arithmetic and Logic Units (ALUs)
      • Three Internal Data or Operand Read Buses and Two Write Buses
      • Software-Compatible with C55x Devices
      • Industrial Temperature Devices Available
    • 320KB of Zero-Wait State On-Chip RAM:
      • 64KB of Dual-Access RAM (DARAM),
        8 Blocks of 4K x 16-Bit
      • 256KB of Single-Access RAM (SARAM),
        32 Blocks of 4K x 16-Bit
    • 128KB of Zero Wait-State On-Chip ROM
      (4 Blocks of 16K x 16-Bit)
    • Tightly Coupled FFT Hardware Accelerator
  • PERIPHERAL:
    • One Universal Host-Port Interface (UHPI) with 16-Bit Muxed Address or Data Bus
    • Master and Slave Multichannel Serial Ports Interface (McSPI) with Three Chip Selects
    • Master and Slave Multichannel Buffered Serial Ports Interface (McBSP)
    • 16- and 8-Bit External Memory Interface (EMIF) with Glueless Interface to:
      • 8- or 16-Bit NAND Flash, 1- or 4-Bit ECC
      • 8- and 16-Bit NOR Flash
      • Asynchronous Static RAM (SRAM)
      • SDRAM or mSDRAM (1.8, 2.75, and 3.3 V)
    • 3.84375M x 16-Bit Maximum Addressable External Memory Space (SDRAM or mSDRAM)
    • Universal Asynchronous Receiver/Transmitter (UART)
    • Device USB Port with Integrated 2.0 High-Speed PHY that Supports:
      • USB 2.0 Full- and High-Speed Devices
    • Direct Memory Access (DMA) Controller
      • Four DMA with Four Channels Each
    • Three 32-Bit General-Purpose (GP) Timers
      • One Selectable as a Watchdog or GP
      • Clocking Options, Including External General-Purpose I/O (GPIO) Clock Input
    • Two MultiMedia Card and Secure Digital (eMMC, MMC, and SD) Interfaces
    • Serial Port Interface (SPI) with Four Chip Selects
    • Master and Slave Inter-Integrated Circuit (I2C Bus)
    • Three Inter-IC Sound (I2S Bus) Modules for Data Transport
    • 10-Bit 4-Input Successive Approximation (SAR) ADC
    • IEEE-1149.1 (JTAG)
      Boundary-Scan-Compatible
    • Up to 26 GPIO Pins (Multiplexed with Other Functions)
  • POWER:
    • Four Core Isolated Power Supply Domains: Analog, RTC, CPU and Peripherals, and USB
    • Four I/O Isolated Power Supply Domains: RTC I/O, EMIF I/O, USB PHY, and DVDDIO
    • 1.05-V Core, 1.8-, 2.75-, or 3.3-V I/Os
    • 1.3-V Core, 1.8-, 2.75-, or 3.3-V I/Os
    • 1.4-V Core, 1.8-, 2.75-, or 3.3-V I/Os
  • CLOCK:
    • Real-Time Clock (RTC) with Crystal Input, Separate Clock Domain, and Power Supply
    • Software-Programmable Phase-Locked Loop (PLL) Clock Generator
  • BOOTLOADER:
    • On-Chip ROM Bootloader
      • Each Peripheral Supports Unencrypted Booting
  • PACKAGE:
    • 196-Terminal Pb-Free Plastic BGA (Ball Grid Array) (ZCH Suffix), 0.65-mm Pitch

All trademarks are the property of their respective owners. All trademarks are the property of their respective owners.

  • CORE:
    • High-Performance, Low-Power, TMS320C55x Fixed-Point Digital Signal Processor
      • 13.33- to 5-ns Instruction Cycle Time
      • 75- to 200-MHz Clock Rate
      • One or Two Instructions Executed per Cycle
      • Dual Multiply-and-Accumulate Units (Up to 450 Million Multiply-Accumulates per Second [MMACS])
      • Two Arithmetic and Logic Units (ALUs)
      • Three Internal Data or Operand Read Buses and Two Write Buses
      • Software-Compatible with C55x Devices
      • Industrial Temperature Devices Available
    • 320KB of Zero-Wait State On-Chip RAM:
      • 64KB of Dual-Access RAM (DARAM),
        8 Blocks of 4K x 16-Bit
      • 256KB of Single-Access RAM (SARAM),
        32 Blocks of 4K x 16-Bit
    • 128KB of Zero Wait-State On-Chip ROM
      (4 Blocks of 16K x 16-Bit)
    • Tightly Coupled FFT Hardware Accelerator
  • PERIPHERAL:
    • One Universal Host-Port Interface (UHPI) with 16-Bit Muxed Address or Data Bus
    • Master and Slave Multichannel Serial Ports Interface (McSPI) with Three Chip Selects
    • Master and Slave Multichannel Buffered Serial Ports Interface (McBSP)
    • 16- and 8-Bit External Memory Interface (EMIF) with Glueless Interface to:
      • 8- or 16-Bit NAND Flash, 1- or 4-Bit ECC
      • 8- and 16-Bit NOR Flash
      • Asynchronous Static RAM (SRAM)
      • SDRAM or mSDRAM (1.8, 2.75, and 3.3 V)
    • 3.84375M x 16-Bit Maximum Addressable External Memory Space (SDRAM or mSDRAM)
    • Universal Asynchronous Receiver/Transmitter (UART)
    • Device USB Port with Integrated 2.0 High-Speed PHY that Supports:
      • USB 2.0 Full- and High-Speed Devices
    • Direct Memory Access (DMA) Controller
      • Four DMA with Four Channels Each
    • Three 32-Bit General-Purpose (GP) Timers
      • One Selectable as a Watchdog or GP
      • Clocking Options, Including External General-Purpose I/O (GPIO) Clock Input
    • Two MultiMedia Card and Secure Digital (eMMC, MMC, and SD) Interfaces
    • Serial Port Interface (SPI) with Four Chip Selects
    • Master and Slave Inter-Integrated Circuit (I2C Bus)
    • Three Inter-IC Sound (I2S Bus) Modules for Data Transport
    • 10-Bit 4-Input Successive Approximation (SAR) ADC
    • IEEE-1149.1 (JTAG)
      Boundary-Scan-Compatible
    • Up to 26 GPIO Pins (Multiplexed with Other Functions)
  • POWER:
    • Four Core Isolated Power Supply Domains: Analog, RTC, CPU and Peripherals, and USB
    • Four I/O Isolated Power Supply Domains: RTC I/O, EMIF I/O, USB PHY, and DVDDIO
    • 1.05-V Core, 1.8-, 2.75-, or 3.3-V I/Os
    • 1.3-V Core, 1.8-, 2.75-, or 3.3-V I/Os
    • 1.4-V Core, 1.8-, 2.75-, or 3.3-V I/Os
  • CLOCK:
    • Real-Time Clock (RTC) with Crystal Input, Separate Clock Domain, and Power Supply
    • Software-Programmable Phase-Locked Loop (PLL) Clock Generator
  • BOOTLOADER:
    • On-Chip ROM Bootloader
      • Each Peripheral Supports Unencrypted Booting
  • PACKAGE:
    • 196-Terminal Pb-Free Plastic BGA (Ball Grid Array) (ZCH Suffix), 0.65-mm Pitch

All trademarks are the property of their respective owners. All trademarks are the property of their respective owners.

This device is a member of TI's C5000 fixed-point Digital Signal Processor (DSP) product family and is designed for low active and standby power consumption.

The device is based on the TMS320C55x DSP generation CPU processor core. The C55x DSP architecture achieves high performance and low power through increased parallelism and total focus on power savings. The CPU supports an internal bus structure that is composed of one program bus, one 32-bit data read bus and two 16-bit data read buses, two 16-bit data write buses, and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to four 16-bit data reads and two 16-bit data writes in a single cycle. The device also includes four DMA controllers, each with 4 channels, providing data movement for 16 independent channel contexts without CPU intervention. Each DMA controller can perform one 32-bit data transfer per cycle, in parallel and independent of the CPU activity.

The C55x CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit x 17-bit multiplication and a 32-bit add in a single cycle. A central 40-bit arithmetic and logic unit (ALU) is supported by an additional 16-bit ALU. Use of the ALUs is under instruction set control, providing the ability to optimize parallel activity and power consumption. These resources are managed in the Address Unit (AU) and Data Unit (DU) of the C55x CPU.

The C55x CPU supports a variable byte width instruction set for improved code density. The Instruction Unit (IU) performs 32-bit program fetches from internal or external memory and queues instructions for the Program Unit (PU). The PU decodes the instructions, directs tasks to the AU and DU resources, and manages the fully protected pipeline. Predictive branching capability avoids pipeline flushes on execution of conditional instructions.

The GPIO functions along with the 10-bit SAR ADC to provide sufficient pins for status, interrupts, and bit I/O for keyboards, and media interfaces.

Serial media is supported through two multimedia card and secure digital (MMC and SD) peripherals, three Inter-IC Sound (I2S Bus) modules, one serial port interface (SPI) with up to four chip selects, one master and slave multichannel serial port interface (McSPI) with up to three chip selects, one multichannel serial port (McBSP), one I2C multimaster and slave interface, and a universal asynchronous receiver/transmitter (UART) interface

The device peripheral set includes an external memory interface (EMIF) that provides glueless access to asynchronous memories, such as EPROM, NOR, NAND, and SRAM, as well as to high-speed, high-density memories such as synchronous DRAM (SDRAM) and mobile SDRAM (mSDRAM).

Additional peripherals include a configurable 16-bit universal host-port interface (UHPI), a high-speed universal serial bus (USB2.0) device mode only, a real-time clock (RTC), three general-purpose timers with one configurable as a watchdog timer, and an analog phase-locked loop (APLL) clock generator.

The device also includes a tightly coupled FFT hardware accelerate that supports 8- to 1024-point (by power of 2) real- and complex-valued FFTs and three integrated LDOs to power different sections of the device, except CVDDRTC which requires an external power source: ANA_LDO to provide 1.3 V to the SAR and power-management circuits (VDDA_ANA), DSP_LDO to provide 1.3 or 1.05 V to the DSP core (CVDD), selectable on-the-fly by software as long as operating frequency ranges are observed, and USB_LDO to provide 1.3 V to the USB core digital (USB_VDD1P3) and PHY circuits (USB_VDDA1P3).

The device is supported by the industry’s award-winning eXpressDSP, Code Composer Studio Integrated Development Environment (IDE), DSP/BIOS, Texas Instruments’ algorithm standard, and a large third-party network. Code Composer Studio IDE features code generation tools including a C Compiler and Linker, RTDX, XDS100, XDS510, XDS560 emulation device drivers, and evaluation modules. The device is also supported by the C55x DSP library which features more than 50 foundational software kernels (FIR filters, IIR filters, FFTs, and various math functions) as well as chip support libraries.

This device is a member of TI's C5000 fixed-point Digital Signal Processor (DSP) product family and is designed for low active and standby power consumption.

The device is based on the TMS320C55x DSP generation CPU processor core. The C55x DSP architecture achieves high performance and low power through increased parallelism and total focus on power savings. The CPU supports an internal bus structure that is composed of one program bus, one 32-bit data read bus and two 16-bit data read buses, two 16-bit data write buses, and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to four 16-bit data reads and two 16-bit data writes in a single cycle. The device also includes four DMA controllers, each with 4 channels, providing data movement for 16 independent channel contexts without CPU intervention. Each DMA controller can perform one 32-bit data transfer per cycle, in parallel and independent of the CPU activity.

The C55x CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit x 17-bit multiplication and a 32-bit add in a single cycle. A central 40-bit arithmetic and logic unit (ALU) is supported by an additional 16-bit ALU. Use of the ALUs is under instruction set control, providing the ability to optimize parallel activity and power consumption. These resources are managed in the Address Unit (AU) and Data Unit (DU) of the C55x CPU.

The C55x CPU supports a variable byte width instruction set for improved code density. The Instruction Unit (IU) performs 32-bit program fetches from internal or external memory and queues instructions for the Program Unit (PU). The PU decodes the instructions, directs tasks to the AU and DU resources, and manages the fully protected pipeline. Predictive branching capability avoids pipeline flushes on execution of conditional instructions.

The GPIO functions along with the 10-bit SAR ADC to provide sufficient pins for status, interrupts, and bit I/O for keyboards, and media interfaces.

Serial media is supported through two multimedia card and secure digital (MMC and SD) peripherals, three Inter-IC Sound (I2S Bus) modules, one serial port interface (SPI) with up to four chip selects, one master and slave multichannel serial port interface (McSPI) with up to three chip selects, one multichannel serial port (McBSP), one I2C multimaster and slave interface, and a universal asynchronous receiver/transmitter (UART) interface

The device peripheral set includes an external memory interface (EMIF) that provides glueless access to asynchronous memories, such as EPROM, NOR, NAND, and SRAM, as well as to high-speed, high-density memories such as synchronous DRAM (SDRAM) and mobile SDRAM (mSDRAM).

Additional peripherals include a configurable 16-bit universal host-port interface (UHPI), a high-speed universal serial bus (USB2.0) device mode only, a real-time clock (RTC), three general-purpose timers with one configurable as a watchdog timer, and an analog phase-locked loop (APLL) clock generator.

The device also includes a tightly coupled FFT hardware accelerate that supports 8- to 1024-point (by power of 2) real- and complex-valued FFTs and three integrated LDOs to power different sections of the device, except CVDDRTC which requires an external power source: ANA_LDO to provide 1.3 V to the SAR and power-management circuits (VDDA_ANA), DSP_LDO to provide 1.3 or 1.05 V to the DSP core (CVDD), selectable on-the-fly by software as long as operating frequency ranges are observed, and USB_LDO to provide 1.3 V to the USB core digital (USB_VDD1P3) and PHY circuits (USB_VDDA1P3).

The device is supported by the industry’s award-winning eXpressDSP, Code Composer Studio Integrated Development Environment (IDE), DSP/BIOS, Texas Instruments’ algorithm standard, and a large third-party network. Code Composer Studio IDE features code generation tools including a C Compiler and Linker, RTDX, XDS100, XDS510, XDS560 emulation device drivers, and evaluation modules. The device is also supported by the C55x DSP library which features more than 50 foundational software kernels (FIR filters, IIR filters, FFTs, and various math functions) as well as chip support libraries.
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技術文件

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重要文件 類型 標題 格式選項 下載最新的英文版本 日期
* 資料表 TMS320C5517 Fixed-Point Digital Signal Processor datasheet (Rev. C) PDF | HTML 2014/4/23
* 勘誤表 TMS320C5517 Fixed-Point DSP Silicon Errata (Rev. B) 2017/9/7
應用說明 How to Migrate CCS 3.x Projects to the Latest CCS (Rev. A) PDF | HTML 2021/5/19
應用說明 Using the TMS320C5517 Bootloader (Rev. A) 2019/11/21
應用說明 C55x CSL Audio Pre-Processing PDF | HTML 2019/6/17
應用說明 TMS320VC5502 to TMS320C5517 Hardware Migration Guide 2018/7/31
應用說明 Sitara Linux ALSA DSP Microphone Array Voice Recognition 2017/6/30
白皮書 Voice as the user interface – a new era in speech processing white Paper 2017/5/9
應用說明 MEMS Microphone Direct PDM Input via I2S to a C5515 EVM With Software Decimation 2016/9/22
應用說明 Usage Guidelines for C55x On-Chip Low Dropout Regulators (LDOs) 2016/7/26
應用說明 Instructions to Benchmark C55 DSP Library 2016/4/1
應用說明 C5000 DSP-Based Low-Power System Design 2015/11/30
應用說明 Power Estimation and Power Consumption summary for TMS320C5517 Device 2015/10/6
使用指南 TMS320C5517 Digital Signal Processor Technical Reference Manual (Rev. B) 2015/9/30
應用說明 Migrating from TMS320C5515 to 5517 2014/4/2
應用說明 Estimating Power Consumption on the TMS320C5517 2014/4/2
應用說明 Validating High- and Full-Speed USB on TMS320C5517 2014/4/2
使用指南 TMS320C55x Optimizing C/C++ Compiler User's Guide (Rev. G) 2011/11/9
使用指南 TMS320C55x Assembly Language Tools User's Guide (Rev. I) 2011/11/9
使用指南 TMS320C55x v3.x DSP Algebraic Instruction Set Reference Guide (Rev. E) 2009/6/24
使用指南 TMS320C55x v3.x DSP Mnemonic Instruction Set Reference Guide (Rev. E) 2009/6/24
使用指南 TMS320C55x DSP v3.x CPU Reference Guide (Rev. E) 2009/6/17

設計與開發

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偵錯探測器

TMDSEMU200-U — XDS200 USB 偵錯探測器

XDS200 是為 TI 嵌入式裝置偵錯的偵錯探測器（模擬器）。對於大多數裝置，建議使用較新、成本較低的 XDS110 (www.ti.com/tool/TMDSEMU110-U)。XDS200 支援單一 Pod 中廣泛的標準（IEEE1149.1、IEEE1149.7、SWD）。所有 XDS 偵錯探針在所有配備嵌入式追蹤緩衝器 (ETB) 的 Arm® 與 DSP 處理器中均支援核心與系統追蹤。

XDS200 透過 TI 20 接腳連接器（配備適用 TI 14 接腳、Arm Cortex® 10 接腳和 Arm 20 接腳的多重轉接器）連接到目標電路板，並透過 USB2.0 高速 (...)

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偵錯探測器

TMDSEMU560V2STM-U — XDS560™ 軟體 v2 系統追蹤 USB 偵錯探測器

XDS560v2 是 XDS560™ 系列偵錯探測器中性能最高的，且同時支援傳統 JTAG 標準 (IEEE1149.1) 與 cJTAG (IEEE1149.7)。  請注意，其不支援序列線偵錯 (SWD)。

所有 XDS 偵錯探測器均在所有配備嵌入式追蹤緩衝器 (ETB) 的 ARM 與 DSP 處理器中支援核心與系統追蹤。  對於針腳上的追蹤，則需要 XDS560v2 PRO TRACE。

XDS560v2 透過 MIPI HSPT 60 針腳接頭 (具有用於 TI 14 針腳、TI 20 針腳和 ARM 20 針腳的多轉接器) 連接到目標電路板，並透過 USB2.0 高速 (...)

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偵錯探測器

TMDSEMU560V2STM-UE — XDS560v2 System Trace USB 與乙太網路偵錯探測器

The XDS560v2 is the highest performance of the XDS560™ family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors (...)

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偵錯探測器

LB-3P-TRACE32-DSP — 適用於數位訊號處理器 (DSP) 的 Lauterbach TRACE32 偵錯和追蹤系統

Lauterbach‘s TRACE32® tools are a suite of leading-edge hardware and software components that enables developers to analyze, optimize and certify all kinds of single- or multi-core Digital Signal processors (DSPs) which are a popular choice for audio and video processing as well as radar data (...)

從：Lauterbach GmbH
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驅動程式或資料庫

AEC-AER — Acoustic echo cancellation/removal for TI C64x+, C674x, C55x and Cortex®-A8 processors

Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be (...)

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驅動程式或資料庫

C55XCSL-LOWPOWER — TMS320C55x Chip Support Library for C5504/05, C5514/15/17 and C5535/45 devices

C55x 晶片支援函式庫 (CSL) 提供了應用程式編程介面 (API)，可用來設定與控制 DSP 晶片內建的週邊設備，以實現易用性、各種 C55x 裝置間的相容性以及硬體抽象。CSL 透過提供標準化和可移植性，可縮短開發時間。

  • C55x CSL (SPRC133)：特性部分列出的函式專門針對 TMS320C55x DSP 設計，包括 C5501、C5502、 C5509、C5509A、C5510 和 C5510A。
  • C55x CSL - 低功耗：特性部分列出的函式專門針對 TMS320C55x 低功耗 DSP 設計，包括 C5504/05、C5514/15/17 及 C5535/45 裝置。

(...)

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驅動程式或資料庫

FAXLIB — FAX library (FAXLIB) for C66x, C64x+ and C55x processors

Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be (...)

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驅動程式或資料庫

SPRC264 — TMS320C5000/6000 映像庫 (IMGLIB)

C5000 6000 影像處理庫 (IMGLIB) 是適合 C 程式設計工具的最佳化影像/影片處理函式庫。此函式庫包括 C 可呼叫通用影像/影片處理常式，這些常式通常用於運算密集型即時應用。相較於同等標準 ANSI C 語言程式碼，使用這些常式可以實現更高性能。IMGLIB 透過立即可用的 DSP 功能與原始程式碼，能夠大幅縮短應用程式開發時間。

查看基準測試：DSP 核心基準測試

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驅動程式或資料庫

VOLIB — Voice library (VoLIB) for C66x, C64x+ and C55x processors

Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be (...)

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軟體轉碼器

ADT-3P-DSPVOIPCODECS — 適應性數位技術 DSP VOIP、語音和音訊轉碼器

Adaptive Digital is a developer of voice quality enhancement algorithms, and best-in-class acoustic echo cancellation software that work with TI DSPs. Adaptive Digital has extensive experience in the algorithm development, implementation, optimization and configuration tuning. They provide (...)
從：Adaptive Digital Technologies, Inc.
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軟體轉碼器

ALGOT-3P-DSPVOIPCODECS — Algotron C5000 DSP 電信和音訊轉碼器

Algotron provides C5000 DSP software modules for telecoms & audio. Examples are: modem data pumps, speech coders, signal generators & detectors for DTMF and caller ID. All modules feature simple yet flexible interfaces with full re-entrancy. They come with user's guides, example (...)

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軟體轉碼器

DSPI-3P-DSPVOIPCODECS — DSP 創新：DSP VoIP 轉碼器

DSP Innovations is a supplier of C5000TM DSP-software and engineering services. Proprietary and standard vocoders from DSPINI have superior characteristics, operate in range from 300 bps up to 64 kbps and are used in: secure voice, software defined radio, wireless, VoIP, voice storage, and more. (...)

從：DSP Innovations
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模擬型號

C5517 ZCH BSDL Model

SPRM631.ZIP (5 KB) - BSDL 模型
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模擬型號

C5517 ZCH IBIS Model

SPRM632.ZIP (902 KB) - IBIS 模型
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參考設計

TIDA-01589 — 具備雜訊消除與回波抵銷功能的高保真、近場雙向音訊參考設計

人機互動需要聲學介面，以提供全雙工免手持通訊。在免手持模式下，來自喇叭的部分遠端或近端音訊訊號會耦合至麥克風。此外，在雜訊環境中，除了可擷取有用的近端音訊訊號外，麥克風還會擷取環境雜訊。擷取的多麥克風音訊訊號會受到聲學背景雜訊及回波訊號破壞，這些訊號會大幅降低所需訊號的清晰度，並限制後續音訊處理系統的性能。此參考設計展示了雙麥克風，其用於透過立體聲 ADC 實現音訊輸入，透過低功耗 DSP 執行雜訊降低、聲音回波消除和其他音訊品質強化演算法。此設計還採用了 TI 智慧型放大器技術，可透過微型喇叭實現高品質、高 SPL 音訊輸出。
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參考設計

TIDEP-0077 — 適用於基於語音的應用的音訊預處理系統參考設計

此參考設計使用多個麥克風、波束成形演算法和其他程序，在雜音和其他干擾中擷提取清晰的語音和音訊。  在易受噪音影響的環境中，使用語音啟動數位助理的應用程式迅速增加，對於能夠在嘈雜環境中擷取清晰語音的系統，其需求也應運而生。  此參考設計採用麥克風陣列與先進訊號處理技術，能從嘈雜環境中擷取清晰音訊。
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參考設計

TIDEP-0083 — 具有 IBM Watson 雲端連線的語音觸發和處理參考設計

此參考設計可讓單一平台展示端對端語音擷取、辨識及處理功能。  它透過預先整合 Sensory 的關鍵字辨識軟體和 IBM Watson Cloud 服務，進一步縮短了應用程式開發時間。此設計也具備彈性的麥克風平台，可根據預期應用雜訊環境進行配置。
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封裝 針腳 CAD 符號、佔位空間與 3D 模型
NFBGA (ZCH) 196 Ultra Librarian
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